These monolithic BCD-to-decimal decoders/drivers consist of eight inverters and ten four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid BCD input logic ensures that all outputs remain off for all invalid binary input conditions. These decoders feature TTL inputs and high-performance, n-p-n output transistors designed for use as indicator/relay drivers or as open-collector logic-circuit drivers. Each of the high-breakdown output transistors (30 volts) will sink up to 80 milliamperes of current. Each input is one normalized Series 54 /74 load. Inputs and outputs are entirely compatible for use with TTL logic circuits, and the outputs are compatible for interfacing with most MOS integrated circuits. Power dissipation is typically 215 milliwatts.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | BCD-to-Decimal Decoders/Drivers datasheet | 01 Mar 1988 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Oct 1996 | ||
| Application note | Live Insertion | 01 Oct 1996 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| PDIP (N) | 16 | Ultra Librarian |
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