SN74AHC1G86

Name: SN74AHC1G86
Brand: TI
SKU: SN74AHC1G86
Price: 0.022 USD

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Single 2-input, 2-V to 5.5-V XOR (exclusive OR) gate

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Data sheet

document-pdfAcrobat SN74AHC1G86 Single 2-Input Exclusive-OR Gate datasheet (Rev. P) PDF | HTML

SN74AHC1G86

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Data sheet

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Product details

Technology family

AHC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

8

Input type

Standard CMOS

IOH (max) (mA)

-8

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

110

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

AHC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

8

Input type

Standard CMOS

IOH (max) (mA)

-8

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

110

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SOT-23 (DBV)

5

8.12 mm² 2.9 x 2.8

SOT-5X3 (DRL)

5

2.56 mm² 1.6 x 1.6

SOT-SC70 (DCK)

5

4.2 mm² 2 x 2.1

Operating range of 2V to 5.5V
Max tpd of 8ns at 5V
Low power consumption, 10µA max ICC
±8mA output drive at 5V
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time
Latch-up performance exceeds 250mA per JESD 17

Operating range of 2V to 5.5V
Max tpd of 8ns at 5V
Low power consumption, 10µA max ICC
±8mA output drive at 5V
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time
Latch-up performance exceeds 250mA per JESD 17

The SN74AHC1G86 is a single 2-input exclusive-OR gate. The device performs the Boolean function Y = A × B or Y = AB + A B in positive logic.

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SN74LVC1G86

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Single 2-input, 1.65-V to 5.5-V XOR (exclusive OR) gate Shorter average propagation delay (5.5ns), higher average drive strength (24mA)

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	Type	Title		Date
*	Data sheet	SN74AHC1G86 Single 2-Input Exclusive-OR Gate datasheet (Rev. P)	PDF \| HTML	07 Feb 2024
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Selection guide	Little Logic Guide 2018 (Rev. G)		06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dec 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 Jun 2004
	Application note	Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)		02 Dec 2002
	Application note	Texas Instruments Little Logic Application Report		01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	Design guide	AHC/AHCT Designer's Guide February 2000 (Rev. D)		24 Feb 2000
	Application note	Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)		08 Sep 1999
	Product overview	Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)		01 Apr 1998
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		01 Dec 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	Live Insertion		01 Oct 1996