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SN74LV21A

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2-ch, 4-input 2-V to 5.5-V high-speed (7 ns) AND gate

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Data sheet

SN74LV21A

ACTIVE
Data sheet Order now

Product details

Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 2 Inputs per channel 4 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 2 Inputs per channel 4 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4
  • 2-V to 5.5-V V CC Operation
  • Max t pd of 6 ns at 5 V
  • Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, TA = 25°C
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • 2-V to 5.5-V V CC Operation
  • Max t pd of 6 ns at 5 V
  • Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, TA = 25°C
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

These dual 4-input positive-AND gates are designed for 2-V to 5.5-V V CC operation.

The SN74LV21A devices perform the Boolean function Y = A • B • C • D in positive logic.

These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

These dual 4-input positive-AND gates are designed for 2-V to 5.5-V V CC operation.

The SN74LV21A devices perform the Boolean function Y = A • B • C • D in positive logic.

These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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Technical documentation

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* Data sheet SN74LV21A Dual 4-Input Positive-AND Gate datasheet (Rev. F) PDF | HTML 14 Jul 2023

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LV21A IBIS Model

SCEM793.ZIP (46 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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