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SN74LV2T74-EP

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Enhanced-product dual D-type flip-flops with clear, preset and integrated level shifter

SN74LV2T74-EP

ACTIVE

Product details

Technology family LVxT Number of channels 2 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type Standard CMOS, TTL-Compatible CMOS Output type Push-Pull Operating temperature range (°C) -55 to 125
Technology family LVxT Number of channels 2 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type Standard CMOS, TTL-Compatible CMOS Output type Push-Pull Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Wide operating range of 1.8 V to 5.5 V
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:

      • 1.2 V to 1.8 V
      • 1.5 V to 2.5 V
      • 1.8 V to 3.3 V
      • 3.3 V to 5.0 V
    • Down translation:
      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17
  • Supports defense, aerospace, and medical applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability
  • Wide operating range of 1.8 V to 5.5 V
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:

      • 1.2 V to 1.8 V
      • 1.5 V to 2.5 V
      • 1.8 V to 3.3 V
      • 3.3 V to 5.0 V
    • Down translation:
      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17
  • Supports defense, aerospace, and medical applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability

The SN74LV2T74-EP contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN74LV2T74-EP contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

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Technical documentation

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Type Title Date
* Data sheet SN74LV2T74-EP Enhanced Product, Dual D-Type Flip-Flop With Integrated Translation datasheet PDF | HTML 15 Nov 2023
* Radiation & reliability report SN74LV2T74-EP Enhanced Product Qualification and Reliability Report PDF | HTML 20 Nov 2023

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
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TSSOP (PW) 14 Ultra Librarian

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