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SN74LV373A

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Octal transparent D-type latches with 3-state outputs

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Data sheet

SN74LV373A

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Catalog
SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SOP (NS) 20 98.28 mm² 12.6 x 7.8 SSOP (DB) 20 56.16 mm² 7.2 x 7.8 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4 VQFN (RGY) 20 15.75 mm² 4.5 x 3.5
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 8.5 ns at 5 V
  • Typical V OLP (Output Ground Bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 8.5 ns at 5 V
  • Typical V OLP (Output Ground Bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

The SN74LV373A device is an octal transparent D-type latch designed for 2 V to 5.5 V V CC operation.

The SN74LV373A device is an octal transparent D-type latch designed for 2 V to 5.5 V V CC operation.
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Technical documentation

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Type Title Date
* Data sheet SN74LV373A Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. N) PDF | HTML 04 Dec 2023
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LV373A IBIS Model (Rev. A)

SCEM141A.ZIP (18 KB) - IBIS Model
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Reference designs

TIDM-TM4CFLASHSRAM — Concurrent Parallel XIP Flash and SRAM Design for code download & execution on High Performance MCUs

This reference design demonstrates how to implement and interface Asynchronous Parallel Flash and SRAM Memories to the performance microcontroller TM4C129. The implementation is made possible by using the EPI Interface in Host Bus 16 Mode with mutliple Chip Selects to interface a 1Gbit-8Mbit range (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
SOIC (DW) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
VQFN (RGY) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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