Home Power management Gate drivers Isolated gate drivers
Home
Power management
Gate drivers
Isolated gate drivers

UCC21551-Q1

ACTIVE

Automotive, 4A/6A 5kVRMS dual-channel isolated gate driver with EN and DT pins for IGBT and SiC

Order now
Data sheet

UCC21551-Q1

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Isolation rating Reinforced Withstand isolation voltage (VISO) (Vrms) 5000 Transient isolation voltage (VIOTM) (VPK) 7070 TI functional safety category Functional Safety-Capable Power switch IGBT, MOSFET, SiCFET Features Enable, High CMTI, Programmable dead time Output VCC/VDD (max) (V) 25 Output VCC/VDD (min) (V) 13 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 150 Rating Automotive Fall time (ns) 8 Undervoltage lockout (typ) (V) 5, 8, 12, 17
Number of channels 2 Isolation rating Reinforced Withstand isolation voltage (VISO) (Vrms) 5000 Transient isolation voltage (VIOTM) (VPK) 7070 TI functional safety category Functional Safety-Capable Power switch IGBT, MOSFET, SiCFET Features Enable, High CMTI, Programmable dead time Output VCC/VDD (max) (V) 25 Output VCC/VDD (min) (V) 13 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 150 Rating Automotive Fall time (ns) 8 Undervoltage lockout (typ) (V) 5, 8, 12, 17
SOIC (DW) 16 106.09 mm² 10.3 x 10.3 SOIC (DWK) 14 106.09 mm² 10.3 x 10.3 SSOP (DFJ) 28 109.18 mm² 10.6 x 10.3
  • Universal: dual low-side, dual high-side or half-bridge driver
  • AEC-Q100 qualified with the following result
    • Device temperature grade 1
  • Junction temperature range –40 to +150°C
  • Up to 4A peak source and 6A peak sink output
  • Common-mode transient immunity (CMTI) greater than 125V/ns
  • CH-to-CH creepage:
    • >5.3mm in DFJ28 package
    • >3.3mm in DWK package
  • Up to 25V VDD output drive supply
    • 5V,8V, 12V and 17V VDD UVLO options
  • Switching parameters:
    • 33ns typical propagation delay
    • 5ns maximum pulse-width distortion
    • 10µs maximum VDD power-up delay
  • UVLO protection for all power supplies
  • Fast enable for power sequencing
  • Universal: dual low-side, dual high-side or half-bridge driver
  • AEC-Q100 qualified with the following result
    • Device temperature grade 1
  • Junction temperature range –40 to +150°C
  • Up to 4A peak source and 6A peak sink output
  • Common-mode transient immunity (CMTI) greater than 125V/ns
  • CH-to-CH creepage:
    • >5.3mm in DFJ28 package
    • >3.3mm in DWK package
  • Up to 25V VDD output drive supply
    • 5V,8V, 12V and 17V VDD UVLO options
  • Switching parameters:
    • 33ns typical propagation delay
    • 5ns maximum pulse-width distortion
    • 10µs maximum VDD power-up delay
  • UVLO protection for all power supplies
  • Fast enable for power sequencing

The UCC21551x-Q1 is an isolated dual channel gate driver family with programmable dead time and wide temperature range. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, SiC, and IGBT transistors.

The UCC21551x-Q1 can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI). DFJ28 package offers >5.3mm CH-to-CH creepage to support high voltage systems.

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5ns. All supplies have UVLO protection.

With all these advanced features, the UCC21551x-Q1 device enables high efficiency, high power density, and robustness in a wide variety of power applications.

The UCC21551x-Q1 is an isolated dual channel gate driver family with programmable dead time and wide temperature range. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, SiC, and IGBT transistors.

The UCC21551x-Q1 can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI). DFJ28 package offers >5.3mm CH-to-CH creepage to support high voltage systems.

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5ns. All supplies have UVLO protection.

With all these advanced features, the UCC21551x-Q1 device enables high efficiency, high power density, and robustness in a wide variety of power applications.
filter Find other Isolated gate drivers
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 5
Type Title Date
* Data sheet UCC21551x-Q1 Automotive 4A, 6A, Reinforced Isolation Dual-Channel Gate Driver datasheet (Rev. H) PDF | HTML 04 Oct 2024
Application note Design Considerations for the Automotive PTC Header Module PDF | HTML 17 Dec 2024
Certificate CQC Certificate for UCC21551xx 27 Aug 2024
Certificate VDE Certificate for Reinforced Isolation for DIN EN IEC 60747-17 (Rev. S) 29 Feb 2024
Functional safety information UCC21551x-Q1 Functional Safety FIT Rate, FMD and Pin FMA PDF | HTML 13 Sep 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

UCC21551CQEVM-079 — UCC21551 evaluation module for 4-A, 6-A dual-channel isolated gate driver

The UCC21551CQEVM has a two-layer copper PCB containing multiple test points and jumpers in order to fully evaluate the functionality of the UCC21551. The EVM features PWM input control, onboard adjustable power supply, sockets for discrete FETs, external active clamp for low-side protection, (...)

User guide: PDF | HTML
Not available on TI.com
Simulation model

UCC21551-Q1 PSpice Transient Reference Design Model

SLUM866.ZIP (175 KB) - PSpice Model
Download
Simulation model

UCC21551-Q1 TINA-TI Reference Design

SLUM863.TSC (9409 KB) - TINA-TI Reference Design
Download
Schematic

UCC21551 Schematic and Layout Design Guidelines

SZZM003.ZIP (1554 KB)
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins CAD symbols, footprints & 3D models
SOIC (DW) 16 Ultra Librarian
SOIC (DWK) 14 Ultra Librarian
SSOP (DFJ) 28 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos