GUI for evaluation module (EVM)
ADC12QJ1600
Quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator
Data sheet
ADC12QJ1600
- ADC Core:
- Resolution: 12 Bit
- Maximum sampling rate: 1.6GSPS
- Non-interleaved architecture
- Internal dither reduces high-order harmonics
- Performance specifications (–1dBFS):
- SNR (100MHz): 57.4dBFS
- ENOB (100MHz): 9.1 Bits
- SFDR (100MHz): 64dBc
- Noise floor (–20dBFS): –147dBFS
- Full-scale input voltage: 80mVPP-DIFF
- Full-power input bandwidth: 6GHz
- JESD204C Serial data interface:
- Support for 2 to 8 (Quad, Dual channel) or 1 to 4 (Single channel) total SerDes lanes
- Maximum baud-rate: 17.16Gbps
- 64B/66B and 8B/10B encoding modes
- Subclass-1 support for deterministic latency
- Compatible with JESD204B receivers
- Optional internal sampling clock generation
- Internal PLL and VCO (7.2 to 8.2GHz)
- SYSREF Windowing eases synchronization
- Four clock outputs simplify system clocking
- Reference clocks for FPGA or adjacent ADC
- Reference clock for SerDes transceivers
- Timestamp input and output for pulsed systems
- Power consumption (1GSPS):
- Quad Channel: 477mW/channel
- Dual channel: 700mW/channel
- Single channel: 1000mW
- Power supplies: 1.1V, 1.9V
ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600 suited for a variety of multi-channel communications and test systems.
Full-power input bandwidth (−3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
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Technical documentation
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View all 2 | Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADC12xJ1600 Quad, Dual, or Single Channel 1.6GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) | PDF | HTML | 06 Nov 2024 |
| Application brief | Time of Flight and LIDAR - Optical Front End Design (Rev. A) | PDF | HTML | 29 Apr 2022 |
Design & development
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Evaluation board
ADC12QJ1600EVM — ADC12QJ1600 evaluation module for quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface
The ADC12QJ1600 evaluation module (EVM) allows for the evaluation of the ADC12QJ1600-Q1 product. ADC12QJ1600-Q1 is a low-power, 12-bit, quad-channel, 1.6-GSPS analog-to-digital converter (ADC) with a buffered analog input and integrated digital down converter with on-chip PLL, which features a (...)
User guide: PDF
Evaluation board
TSW12QJ1600EVM — ADC12QJ1600-Q1 8-ch (two synchronized 4-ch) 12-bit 1.6-GSPS JESD204C interface ADC evaluation module
The TSW12QJ1600 evaluation module (EVM) is used to evaluate the ADC12QJ1600-Q1 analog-to-digital converter (ADC) with different front-end options. ADC12QJ1600-Q1 is a 12-bit ADC capable of operating at sampling rates up to 1.6 gigasample per second (GSPS) with four analog input channels.
This design (...)
User guide: PDF
Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
Ordering & quality
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