Home Logic & voltage translation Flip-flops, latches & registers JK flip-flops
Home
Logic & voltage translation
Flip-flops, latches & registers
JK flip-flops

CD54AC109

ACTIVE

Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset

Order now
Data sheet

CD54AC109

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family AC Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 100 Supply current (max) (µA) 80 IOL (max) (mA) -24 IOH (max) (mA) 24 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Positive edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family AC Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 100 Supply current (max) (µA) 80 IOL (max) (mA) -24 IOH (max) (mA) 24 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Positive edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Balanced propagation delays
  • ±24mA output drive current
    • Fanout to 15 F devices
  • SCR-latchup-resistant CMOS process and circuit design
  • Exceeds 2kV ESD protection per MIL-STD-883, method 3015
  • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Balanced propagation delays
  • ±24mA output drive current
    • Fanout to 15 F devices
  • SCR-latchup-resistant CMOS process and circuit design
  • Exceeds 2kV ESD protection per MIL-STD-883, method 3015

The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.

The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.
filter Find other JK flip-flops
Download

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet CDx4AC109 Dual J- K Positive-Edge-Triggered Flip-flops with Clear and Preset datasheet (Rev. A) PDF | HTML 31 Dec 2024

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​