Gehäuseinformationen
| Gehäuse | Pins SOT-23 (DBV) | 5 |
| Betriebstemperaturbereich (°C) -40 to 125 |
| Gehäusemenge | Träger 3.000 | LARGE T&R |
Merkmale von SN74LV1T126-Q1
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AEC-Q100 qualified for automotive applications:
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Device temperature grade 1: -40°C to +125°C
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Device HBM ESD classification level 2
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Device CDM ESD classification level C4B
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- Wide operating range of 1.8 V to 5.5 V
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Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
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Up translation:
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1.2 V to 1.8 V
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1.5 V to 2.5 V
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1.8 V to 3.3 V
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3.3 V to 5.0 V
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Down translation:
- 5.0 V, 3.3 V, 2.5 V to 1.8 V
- 5.0 V, 3.3 V to 2.5 V
- 5.0 V to 3.3 V
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- 5.5-V tolerant input pins
- Supports standard pinouts
- Up to 150 Mbps with 5-V or 3.3-V V CC
- Latch-up performance exceeds 250 mA per JESD 17
Beschreibung von SN74LV1T126-Q1
The SN74LV1T126-Q1 is a single buffer gate with 3-state outputs and integrated voltage translation. This buffer performs the Boolean function Y = A in positive logic. The outputs can be placed into a Hi-Z state by applying a Low on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).