CDCVF2505

Name: CDCVF2505
Brand: TI
SKU: CDCVF2505
Price: 1.323 USD

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Controlador de reloj PLL para sincronización. DRAM y aplicaciones de uso general con compatibilidad

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document-pdfAcrobat CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver datasheet (Rev. G) (Inglés) PDF | HTML

CDCVF2505

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Detalles del producto

Function

Memory interface

Additive RMS jitter (typ) (fs)

70

Output frequency (max) (MHz)

200

Number of outputs

4

Output supply voltage (V)

3.3

Core supply voltage (V)

3.3

Output skew (ps)

150

Features

SDR

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVCMOS

Input type

LVCMOS

Function

Memory interface

Additive RMS jitter (typ) (fs)

70

Output frequency (max) (MHz)

200

Number of outputs

4

Output supply voltage (V)

3.3

Core supply voltage (V)

3.3

Output skew (ps)

150

Features

SDR

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVCMOS

Input type

LVCMOS

SOIC (D)

8

29.4 mm² 4.9 x 6

TSSOP (PW)

8

19.2 mm² 3 x 6.4

Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications
Spread Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
Low Jitter (Cycle-to-Cycle): < |150 ps| (Over 66 MHz to 200 MHz Range)
Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Used to Tune the Input-Output Delay)
Three-States Outputs When There Is No Input Clock
Operates From Single 3.3-V Supply
Available in 8-Pin TSSOP and 8-Pin SOIC Packages
Consumes Less Than 100 mA (Typical) in Power-Down Mode
Internal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock
25-Ω On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates the Need for External Components

Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications
Spread Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
Low Jitter (Cycle-to-Cycle): < |150 ps| (Over 66 MHz to 200 MHz Range)
Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Used to Tune the Input-Output Delay)
Three-States Outputs When There Is No Input Clock
Operates From Single 3.3-V Supply
Available in 8-Pin TSSOP and 8-Pin SOIC Packages
Consumes Less Than 100 mA (Typical) in Power-Down Mode
Internal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock
25-Ω On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates the Need for External Components

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN.

The loop filter for the PLLs is included on-chip. This minimizes the component count, space, and cost.

The CDCVF2505 is characterized for operation from –40°C to 85°C.

Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN.

The loop filter for the PLLs is included on-chip. This minimizes the component count, space, and cost.

The CDCVF2505 is characterized for operation from –40°C to 85°C.

Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

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Documentación técnica

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	Tipo	Título		Fecha
*	Data sheet	CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver datasheet (Rev. G)	PDF \| HTML	31 ago 2016
	Application note	Design and Layout Guidelines for the CDCVF2505 Clock Driver (Rev. A)		07 mar 2005

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

CDCVF2505 IBIS Model (Rev. B)

SCAC027B.ZIP (15 KB) - IBIS Model

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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
SOIC (D)	8	Ultra Librarian
TSSOP (PW)	8	Ultra Librarian

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CDCVF2505

Controlador de reloj PLL para sincronización. DRAM y aplicaciones de uso general con compatibilidad

CDCVF2505

Detalles del producto

Documentación técnica

Diseño y desarrollo

CDCVF2505 IBIS Model (Rev. B)

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

Videos