SN54HC195

ACTIVO

Registros de desplazamiento de acceso paralelo de 4 bits

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Detalles del producto

Technology family HC Operating temperature range (°C) -55 to 125 Rating Military
Technology family HC Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Synchronous Parallel Load
  • Positive-Edge-Triggered Clocking
  • J and K Inputs to First Stage
  • Complementary Outputs From Last Stage
  • Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers
  • Dependable Texas lnstruments Quality and Reliability

  • Synchronous Parallel Load
  • Positive-Edge-Triggered Clocking
  • J and K Inputs to First Stage
  • Complementary Outputs From Last Stage
  • Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers
  • Dependable Texas lnstruments Quality and Reliability

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).

Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table.

The SN54HC195 is characterized for operation over the full military temperature range of –55°C to 125°C.

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).

Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table.

The SN54HC195 is characterized for operation over the full military temperature range of –55°C to 125°C.

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Documentación técnica

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* Data sheet 4-Bit Parallel-Access Shift Registers datasheet (Rev. A) 16 nov 2007

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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