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Circuitos integrados LVDS, M-LVDS y PECL

SN65LVDM31

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Controlador LVDM cuádruple

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SN65LVDM31

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Detalles del producto

Function Driver Protocols LVDM, LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 150 Input signal LVCMOS Output signal LVDM Rating Catalog Operating temperature range (°C) -40 to 85
Function Driver Protocols LVDM, LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 150 Input signal LVCMOS Output signal LVDM Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Designed for Signaling Rates Up to 150 Mbps
  • Low-Voltage Differential Signaling With Typical Output Voltage of 700 mV and a 100- Load
  • Propagation Delay Time of 2.3 ns, Typical
  • Single 3.3-V Supply Operation
  • One Driver's Power Dissipation at 75 MHz, 50 mW, Typical
  • High-Impedance Outputs When Disabled or With VCC < 1.5 V
  • Bus-Pin ESD Protection Exceeds 12 kV
  • Low-Voltage CMOS (LVCMOS) Logic Input Levels Are 5-V Tolerant

The signaling rate is the number of voltage transitions that can be made per second.
  • Designed for Signaling Rates Up to 150 Mbps
  • Low-Voltage Differential Signaling With Typical Output Voltage of 700 mV and a 100- Load
  • Propagation Delay Time of 2.3 ns, Typical
  • Single 3.3-V Supply Operation
  • One Driver's Power Dissipation at 75 MHz, 50 mW, Typical
  • High-Impedance Outputs When Disabled or With VCC < 1.5 V
  • Bus-Pin ESD Protection Exceeds 12 kV
  • Low-Voltage CMOS (LVCMOS) Logic Input Levels Are 5-V Tolerant

The signaling rate is the number of voltage transitions that can be made per second.

The SN65LVDM31 incorporates four differential line drivers that implement the electrical characteristics of low-voltage differential signaling. This product offers a low-power alternative to 5-V PECL drivers with similar signal levels. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 540 mV into a 100- load when enabled by either an active-low or active-high enable input.

The intended application of this device and signaling technique is for both point-to-point and multiplexed baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDM31 is characterized for operation from -40°C to 85°C.

The SN65LVDM31 incorporates four differential line drivers that implement the electrical characteristics of low-voltage differential signaling. This product offers a low-power alternative to 5-V PECL drivers with similar signal levels. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 540 mV into a 100- load when enabled by either an active-low or active-high enable input.

The intended application of this device and signaling technique is for both point-to-point and multiplexed baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDM31 is characterized for operation from -40°C to 85°C.
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Documentación técnica

star =Principal documentación para este producto seleccionada por TI
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Tipo Título Fecha
* Data sheet High Speed Differential Line Driver datasheet (Rev. C) 06 feb 2002
Application note An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) PDF | HTML 22 jun 2023
Application brief How Far, How Fast Can You Operate MLVDS? 06 ago 2018
User guide Low Voltage Differential Signaling (LVDS) Evaluation Module (EVM) for Quad Drive (Rev. C) 16 feb 2010
Application note SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) 20 nov 2001
Application note An Overview of LVDS Technology 05 oct 1998

Diseño y desarrollo

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Modelo de simulación

SN65LVDM31 IBIS Model

SLLC092.ZIP (4 KB) - IBIS Model
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PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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Pedidos y calidad

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