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SN65LVDS179-EP

ACTIVO

Controladores y receptores de línea diferencial de alta velocidad de producto mejorado

Detalles del producto

Function Transceiver Protocols LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVDS, LVTTL Output signal LVDS, LVTTL Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Function Transceiver Protocols LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVDS, LVTTL Output signal LVDS, LVTTL Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Meet or Exceed the Requirements of ANSI TIA/EIA-644-1995 Standard
  • Signaling Rates up to 400 Mbps
  • Bus-Terminal ESD Exceeds 12 kV
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 100- Load
  • Propagation Delay Times
    • Driver: 1.7 ns Typ
    • Receiver: 3.7 ns Typ
  • Power Dissipation at 200 MHz
    • Driver: 25 mW Typical
    • Receiver: 60 mW Typical
  • LVTTL Input Levels Are 5-V Tolerant
  • Receiver Maintains High Input Impedance With VCC < 1.5 V
  • Receiver Has Open-Circuit Fail Safe

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Meet or Exceed the Requirements of ANSI TIA/EIA-644-1995 Standard
  • Signaling Rates up to 400 Mbps
  • Bus-Terminal ESD Exceeds 12 kV
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 100- Load
  • Propagation Delay Times
    • Driver: 1.7 ns Typ
    • Receiver: 3.7 ns Typ
  • Power Dissipation at 200 MHz
    • Driver: 25 mW Typical
    • Receiver: 60 mW Typical
  • LVTTL Input Levels Are 5-V Tolerant
  • Receiver Maintains High Input Impedance With VCC < 1.5 V
  • Receiver Has Open-Circuit Fail Safe

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100- load, and receipt of 100-mV signals with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100- characteristic impedance. The transmission media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.)

The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state, but rather disconnects the input and reduces the quiescent power used by the device. (For these functions with a high-impedance driver output, see the SN65LVDM series of devices.) All devices are characterized for operation from -55°C to 125°C.

The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100- load, and receipt of 100-mV signals with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100- characteristic impedance. The transmission media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.)

The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state, but rather disconnects the input and reduces the quiescent power used by the device. (For these functions with a high-impedance driver output, see the SN65LVDM series of devices.) All devices are characterized for operation from -55°C to 125°C.

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Documentación técnica

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Tipo Título Fecha
* Data sheet SN65LVDS179-EP, SN65LVDS180-EP, SN65LVDS050-EP, SN65LVDS051-EP datasheet (Rev. B) 16 ene 2007
* Radiation & reliability report SN65LVDS179MDGKREP Reliability Report 14 mar 2018
* VID SN65LVDS179-EP VID V6207612 21 jun 2016
Application brief LVDS to Improve EMC in Motor Drives 27 sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 ago 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 may 2018

Diseño y desarrollo

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Modelo de simulación

SN65LVDS179 IBIS Model Version 2.1 (Rev. A)

SLLM005A.ZIP (5 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
VSSOP (DGK) 8 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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