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データ・コンバータ
A/D コンバータ (ADC)
高速 ADC（≧10 MSPS）

ADS808

生産中止品

12ビット、70MSPS ADC SE/差動、内部/外部リファレンス、フレキシブルクロック　選択、フルスケール・レンジ、パワーダウン

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データシート

ADS808

生産中止品
データシート ご注文はこちら

製品詳細

Sample rate (max) (Msps) 70 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 1, 2 Power consumption (typ) (mW) 720 Architecture Pipeline SNR (dB) 64 ENOB (Bits) 10.3 SFDR (dB) 68 Operating temperature range (°C) to Input buffer No
Sample rate (max) (Msps) 70 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 1, 2 Power consumption (typ) (mW) 720 Architecture Pipeline SNR (dB) 64 ENOB (Bits) 10.3 SFDR (dB) 68 Operating temperature range (°C) to Input buffer No
HTQFP (PHP) 48 81 mm² 9 x 9
  • DYNAMIC RANGE:
        SNR: 64dB at 10MHz fIN
        SFDR: 68dB at 10MHz fIN
  • PREMIUM TRACK-AND-HOLD:
       Low Jitter: 0.25ps rms
       Differential or Single-Ended Inputs
       Selectable Full-Scale Input Range
  • FLEXIBLE CLOCKING:
       Differential or Single-Ended
       Accepts Sine or Square Wave Clocking
       Down to 0.5Vp-p
       Variable Threshold Level
  • APPLICATIONS
    • BASESTATION WIDEBAND RADIOS:
         CDMA, GSM, TDMA, 3G, AMPS, and NMT
    • TEST INSTRUMENTATION
    • CCD IMAGING

PowerPAD is a registered trademark of Texas Instruments.
  • DYNAMIC RANGE:
        SNR: 64dB at 10MHz fIN
        SFDR: 68dB at 10MHz fIN
  • PREMIUM TRACK-AND-HOLD:
       Low Jitter: 0.25ps rms
       Differential or Single-Ended Inputs
       Selectable Full-Scale Input Range
  • FLEXIBLE CLOCKING:
       Differential or Single-Ended
       Accepts Sine or Square Wave Clocking
       Down to 0.5Vp-p
       Variable Threshold Level
  • APPLICATIONS
    • BASESTATION WIDEBAND RADIOS:
         CDMA, GSM, TDMA, 3G, AMPS, and NMT
    • TEST INSTRUMENTATION
    • CCD IMAGING

PowerPAD is a registered trademark of Texas Instruments.

The ADS808 is a high-dynamic range, 12-bit, 70MHz, pipelined Analog-to-Digital Converter (ADC). It includes a high-bandwidth linear track-and-hold that has a low jitter of only 0.25ps rms, leading to excellent SNR performance. The clock input can accept a low-level differential sine wave or square wave signal down to 0.5Vp-p, further improving the SNR performance. It also accepts a single-ended clock signal and has flexible threshold levels.

The ADS808 has a 2Vp-p differential input range (1Vp-p • 2 inputs) for optimum signal-to-noise ratio. The differential operation gives the lowest even-order harmonic components. A lower input voltage of 1.5Vp-p or 1Vp-p can also be selected using the internal references, further optimizing SFDR. Alternatively, a single-ended input range can be used by tying the IN\ input to the common-mode voltage, if desired.

The ADS808 also provides an over-range flag that indicates when the input signal has exceeded the converter’s full-scale range. This flag can also be used to reduce the gain of the front-end signal conditioning circuitry. It also employs digital error-correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS808 is available in a small TQFP-48 PowerPAD™ thermally enhanced package.

The ADS808 is a high-dynamic range, 12-bit, 70MHz, pipelined Analog-to-Digital Converter (ADC). It includes a high-bandwidth linear track-and-hold that has a low jitter of only 0.25ps rms, leading to excellent SNR performance. The clock input can accept a low-level differential sine wave or square wave signal down to 0.5Vp-p, further improving the SNR performance. It also accepts a single-ended clock signal and has flexible threshold levels.

The ADS808 has a 2Vp-p differential input range (1Vp-p • 2 inputs) for optimum signal-to-noise ratio. The differential operation gives the lowest even-order harmonic components. A lower input voltage of 1.5Vp-p or 1Vp-p can also be selected using the internal references, further optimizing SFDR. Alternatively, a single-ended input range can be used by tying the IN\ input to the common-mode voltage, if desired.

The ADS808 also provides an over-range flag that indicates when the input signal has exceeded the converter’s full-scale range. This flag can also be used to reduce the gain of the front-end signal conditioning circuitry. It also employs digital error-correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS808 is available in a small TQFP-48 PowerPAD™ thermally enhanced package.
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* データシート ADS808: 12-Bit, 70MHz Sampling Analog-to-Digital Converter データシート (Rev. C) 2002年 9月 4日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点