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CD74FCT374

アクティブ

3 ステート出力、BiCMOS FCT インターフェイス・ロジック、オクタル D タイプ・フリップ・フロップ

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データシート

CD74FCT374

アクティブ
データシート ご注文はこちら

製品詳細

Number of channels 8 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 48 IOH (max) (mA) -15 Supply current (max) (µA) 80 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 8 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 48 IOH (max) (mA) -15 Supply current (max) (µA) 80 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • BiCMOS Technology With Low Quiescent Power
  • 3-State Outputs Drive Bus Lines Directly
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 48-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
  • Package Options Include Plastic Small-Outline (M) and Shrink Small-Outline (SM) Packages and Standard Plastic (E) DIP
  • BiCMOS Technology With Low Quiescent Power
  • 3-State Outputs Drive Bus Lines Directly
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 48-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
  • Package Options Include Plastic Small-Outline (M) and Shrink Small-Outline (SM) Packages and Standard Plastic (E) DIP

The CD74FCT374 is an octal, edge-triggered, D-type flip-flop that uses a small-geometry BiCMOS technology and features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.

The eight flip-flops enter data into their registers on the low-to-high transition of the clock (CLK). The output-enable (OE\) input controls the 3-state outputs and is independent of the register operation. When OE\ is high, the outputs are in the high-impedance state.

A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD74FCT374 is characterized for operation from 0°C to 70°C.

The CD74FCT374 is an octal, edge-triggered, D-type flip-flop that uses a small-geometry BiCMOS technology and features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.

The eight flip-flops enter data into their registers on the low-to-high transition of the clock (CLK). The output-enable (OE\) input controls the 3-state outputs and is independent of the register operation. When OE\ is high, the outputs are in the high-impedance state.

A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD74FCT374 is characterized for operation from 0°C to 70°C.

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート BiCMOS Octal Edge-Triggered D-Type Flip-Flop With 3-State Outputs データシート 2000年 7月 3日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点

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