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デジタル信号プロセッサ (DSP)

SM320LC31-EP

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データシート

SM320LC31-EP

新規設計での使用を推奨しません
データシート ご注文はこちら

製品詳細

DSP (max) (MHz) 40 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
DSP (max) (MHz) 40 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
QFP (PQ) 132 768.347775 mm² 27.945 x 27.495
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree
  • Operating Temperature Ranges:
    • Military (M) –55°C to 125°C
  • High-Performance Floating-Point Digital Signal Processor (DSP):
    • SM320LC31-40EP (3.3 V)
         50-ns Instruction Cycle Time
         220 MOPS, 40 MFLOPS, 20 MIPS
  • 32-Bit High-Performance CPU
  • 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
  • 32-Bit Instruction and Data Words, 24-Bit Addresses
  • Two 1K Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks
  • Boot-Program Loader
  • 64-Word × 32-Bit Instruction Cache
  • Eight Extended-Precision Registers
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Two Low-Power Modes
  • On-Chip Memory-Mapped Peripherals:
    • One Serial Port Supporting 8-/16-/24-/32-Bit Transfers
    • Two 32-Bit Timers
    • One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
  • Fabricated Using Enhanced Performance Implanted CMOS (EPIC™) Technology by Texas Instruments (TI)
  • Two- and Three-Operand Instructions
  • 40/32-Bit Floating-Point/Integer Multiplier and Arithmetic Logic Unit (ALU)
  • Parallel ALU and Multiplier Execution in a Single Cycle
  • Block-Repeat Capability
  • Zero-Overhead Loops With Single-Cycle Branches
  • Conditional Calls and Returns
  • Interlocked Instructions for Multiprocessing Support
  • Bus-Control Registers Configure Strobe-Control Wait-State Generation
  • Validated Ada Compiler
  • Integer, Floating-Point, and Logical Operations
  • 32-Bit Barrel Shifter
  • One 32-Bit Data Bus (24-Bit Address)
  • Packaging
    • 132-Lead Plastic Quad Flatpack (PQ Suffix)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
EPIC is a trademark of Texas Instruments Incorporated.
All trademarks are the property of their respective owners.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree
  • Operating Temperature Ranges:
    • Military (M) –55°C to 125°C
  • High-Performance Floating-Point Digital Signal Processor (DSP):
    • SM320LC31-40EP (3.3 V)
         50-ns Instruction Cycle Time
         220 MOPS, 40 MFLOPS, 20 MIPS
  • 32-Bit High-Performance CPU
  • 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
  • 32-Bit Instruction and Data Words, 24-Bit Addresses
  • Two 1K Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks
  • Boot-Program Loader
  • 64-Word × 32-Bit Instruction Cache
  • Eight Extended-Precision Registers
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Two Low-Power Modes
  • On-Chip Memory-Mapped Peripherals:
    • One Serial Port Supporting 8-/16-/24-/32-Bit Transfers
    • Two 32-Bit Timers
    • One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
  • Fabricated Using Enhanced Performance Implanted CMOS (EPIC™) Technology by Texas Instruments (TI)
  • Two- and Three-Operand Instructions
  • 40/32-Bit Floating-Point/Integer Multiplier and Arithmetic Logic Unit (ALU)
  • Parallel ALU and Multiplier Execution in a Single Cycle
  • Block-Repeat Capability
  • Zero-Overhead Loops With Single-Cycle Branches
  • Conditional Calls and Returns
  • Interlocked Instructions for Multiprocessing Support
  • Bus-Control Registers Configure Strobe-Control Wait-State Generation
  • Validated Ada Compiler
  • Integer, Floating-Point, and Logical Operations
  • 32-Bit Barrel Shifter
  • One 32-Bit Data Bus (24-Bit Address)
  • Packaging
    • 132-Lead Plastic Quad Flatpack (PQ Suffix)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
EPIC is a trademark of Texas Instruments Incorporated.
All trademarks are the property of their respective owners.

The SM320LC31-EP digital signal processor (DSP) is a 32-bit, floating-point processor manufactured in 0.6-um triple-level-metal CMOS technology. The device is part of the SMJ320C3x generation of DSPs from Texas Instruments.

The SM320LC31-EP internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 60 MFLOPS. The SM320LC31-EP optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

The SM320LC31-EP can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are results of these features.

General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SM320LC31-EP supports a wide variety of system applications from host processor to dedicated coprocessor.

High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001.

The SM320LC31-EP digital signal processor (DSP) is a 32-bit, floating-point processor manufactured in 0.6-um triple-level-metal CMOS technology. The device is part of the SMJ320C3x generation of DSPs from Texas Instruments.

The SM320LC31-EP internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 60 MFLOPS. The SM320LC31-EP optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

The SM320LC31-EP can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are results of these features.

General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SM320LC31-EP supports a wide variety of system applications from host processor to dedicated coprocessor.

High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001.
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* データシート SM320LC31-EP Digital Signal Processor データシート 2002年 9月 19日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
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