SN65LVDS33
- 400-Mbps Signaling Rate1 and 200-Mxfr/s Data Transfer Rate
- Operates With a Single 3.3-V Supply
- –4-V to 5-V Common-Mode Input Voltage Range
- Differential Input Thresholds <±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range
- Integrated 110-
Line Termination Resistors On LVDT Products - TSSOP Packaging (33 Only)
- Complies With TIA/EIA-644 (LVDS)
- Active Failsafe Assures a High-Level Output With No Input
- Bus-Pin ESD Protection Exceeds 15 kV HBM
- Input Remains High-Impedance on Power Down
- TTL Inputs Are 5-V Tolerant
- Pin-Compatible With the AM26LS32, SN65LVDS32B, µA9637, SN65LVDS9637B
1 The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.
Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.
The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.
The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.
The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from –40°C to 85°C.
技術資料
| 種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
|---|---|---|---|---|---|---|
| * | データシート | High Speed Differential Receivers データシート (Rev. B) | 2004年 11月 4日 | |||
| アプリケーション概要 | LVDS to Improve EMC in Motor Drives | 2018年 9月 27日 | ||||
| アプリケーション概要 | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||||
| アプリケーション概要 | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 |
設計および開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
SN65LVDS31-33EVM — 評価モジュール、SN65LVDS31/SN65LVDS33 用
TI offers a series of low-voltage differential signaling (LVDS) evaluation modules (EVMs) designed for analysis of the electrical characteristics of LVDS drivers and receivers. Four unique EVMs are available to evaluate the different classes of LVDS devices offered by TI.
As seen in the Combination (...)
PSPICE-FOR-TI — TI Design / シミュレーション・ツール向け PSpice®
設計とシミュレーション向けの環境である PSpice for TI (...)
TINA-TI — SPICE ベースのアナログ・シミュレーション・プログラム
TINA-TI をインストールするには、約 500MB が必要です。インストールは簡単です。必要に応じてアンインストールも可能です。(そのようなことはないと思いますが)
TINA は DesignSoft (...)
TIDA-060017 — LVDS インターフェイス経由で SPI 信号を送信するリファレンス・デザイン
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点
推奨製品には、この TI 製品に関連するパラメータ、評価基板、またはリファレンス デザインが存在する可能性があります。