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SN74ALVTH16374

生産中止品

3 ステート出力、2.5V/3.3V、16 ビット、エッジ・トリガ D タイプ・フリップ・フロップ

ご注文はこちら
データシート
SN74ALVTH16374 は生産中止品です。
この製品は生産中止品です。新規設計では代替品をご検討ください。
open-in-new 代替品と比較
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74ACT16374 アクティブ 3 ステート出力、16 ビット、D タイプ、エッジ・トリガ・フリップ・フロップ Lower average drive strength (24mA)
SN74ALVCH16374 アクティブ 16 ビット エッジトリガ D タイプ・フリップフロップ、3 ステート出力 Replacement

SN74ALVTH16374

生産中止品
データシート ご注文はこちら

製品詳細

Number of channels 16 Technology family ALVT Supply voltage (min) (V) 2.3 Supply voltage (max) (V) 3.6 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 250 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 16 Technology family ALVT Supply voltage (min) (V) 2.3 Supply voltage (max) (V) 3.6 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 250 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus™ Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • High Drive (-24/24 mA at 2.5-V VCC and -32/64 mA at 3.3-V )
  • Power Off Disables Outputs, Permitting Live Insertion
  • High-Impedance State During Power Up and Power Down Prevents Driver Conflict
  • Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
  • Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection
    • Exceeds 2000 V Per MIL-STD-883, Method 3015
    • Exceeds 200 V Using Machine Model
    • Exceeds 1000 V Using Charged-Device Model, Robotic Method
  • Flow-Through Architecture Facilitates Printed Circuit Board Layout
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

Widebus is a trademark of Texas Instruments.
  • State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus™ Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • High Drive (-24/24 mA at 2.5-V VCC and -32/64 mA at 3.3-V )
  • Power Off Disables Outputs, Permitting Live Insertion
  • High-Impedance State During Power Up and Power Down Prevents Driver Conflict
  • Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
  • Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection
    • Exceeds 2000 V Per MIL-STD-883, Method 3015
    • Exceeds 200 V Using Machine Model
    • Exceeds 1000 V Using Charged-Device Model, Robotic Method
  • Flow-Through Architecture Facilitates Printed Circuit Board Layout
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

Widebus is a trademark of Texas Instruments.

The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ALVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C.

The SN74ALVTH16374 is characterized for operation from -40°C to 85°C.

The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ALVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C.

The SN74ALVTH16374 is characterized for operation from -40°C to 85°C.
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート SN54ALVTH16374, SN74ALVTH16374 データシート (Rev. G) 2006年 11月 9日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点