SN74HCS596

Name: SN74HCS596
Brand: TI
SKU: SN74HCS596
Price: 0.092 USD

アクティブ

8 ビット、シリアル入力 / パラレル出力、シフト・レジスタ

ご注文はこちら

データシート

document-pdfAcrobat SN74HCS596SN74HCS596 8-Bit Shift Register With Schmitt-Trigger Inputs データシート (英語)

SN74HCS596

アクティブ

データシート

ご注文はこちら

製品詳細

Configuration

Serial-in, Parallel-out

Bits (#)

Technology family

HCS

Supply voltage (min) (V)

Supply voltage (max) (V)

Input type

Schmitt-Trigger

Output type

Open-drain

Clock frequency (MHz)

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

Features

Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Configuration

Serial-in, Parallel-out

Bits (#)

Technology family

HCS

Supply voltage (min) (V)

Supply voltage (max) (V)

Input type

Schmitt-Trigger

Output type

Open-drain

Clock frequency (MHz)

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

Features

Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Catalog

SOIC (D)

59.4 mm² 9.9 x 6

TSSOP (PW)

32 mm² 5 x 6.4

Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input signals
Low power consumption
- Typical I_CC of 100 nA
- Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V
Extended ambient temperature range: –40°C to +125°C, T_A

Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input signals
Low power consumption
- Typical I_CC of 100 nA
- Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V
Extended ambient temperature range: –40°C to +125°C, T_A

The SN74HCS596 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (Q_H’) for cascading. When the output-enable (OE) input is high, the outputs are in a highimpedance state. Internal register data is not impacted by the operation of the OE input.