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TL16C754B

アクティブ

64 バイト FIFO 搭載、クワッド UART

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データシート
エラッタ

TL16C754B

アクティブ
データシート ご注文はこちら

製品詳細

Number of channels 4 FIFO (Byte) 64 Rx FIFO trigger levels (#) 16 Tx FIFO trigger levels (#) 16 Programmable FIFO trigger levels Yes CPU interface X86 Baud rate at Vcc = 3.3 V & with 16x sampling (max) (Mbps) 2 Baud rate at Vcc = 5 V & with 16x sampling (max) (Mbps) 3 Operating voltage (V) 3.3, 5 Auto RTS/CTS Yes Rating Catalog Operating temperature range (°C) -40 to 85
Number of channels 4 FIFO (Byte) 64 Rx FIFO trigger levels (#) 16 Tx FIFO trigger levels (#) 16 Programmable FIFO trigger levels Yes CPU interface X86 Baud rate at Vcc = 3.3 V & with 16x sampling (max) (Mbps) 2 Baud rate at Vcc = 5 V & with 16x sampling (max) (Mbps) 3 Operating voltage (V) 3.3, 5 Auto RTS/CTS Yes Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PN) 80 196 mm² 14 x 14 PLCC (FN) 68 632.5225 mm² 25.15 x 25.15
  • ST16C654 Pin Compatible With Additional Enhancements
  • Supports Up To 24-MHz Crystal Input Clock ( 1.5 Mbps)
  • Supports Up To 48-MHz Oscillator Input Clock ( 3 Mbps) for 5-V Operation
  • Supports Up To 32-MHz Oscillator Input Clock ( 2 Mbps) for 3.3-V Operation
  • 64-Byte Transmit FIFO
  • 64-Byte Receive FIFO With Error Flags
  • Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA and Interrupt Generation
  • Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control
  • Software/Hardware Flow Control
    • Programmable Xon/Xoff Characters
    • Programmable Auto-RTS\ and Auto-CTS\
  • Optional Data Flow Resume by Xon Any Character
  • DMA Signalling Capability for Both Received and Transmitted Data
  • Supports 3.3-V or 5-V Supply
  • Characterized for Operation From –40°C to 85°C
  • Software Selectable Baud Rate Generator
  • Prescalable Provides Additional Divide by 4 Function
  • Fast Access 2 Clock Cycle IOR\/IOW\ Pulse Width
  • Programmable Sleep Mode
  • Programmable Serial Interface Characteristics
    • 5, 6, 7, or 8-Bit Characters
    • Even, Odd, or No Parity Bit Generation and Detection
    • 1, 1.5, or 2 Stop Bit Generation
  • False Start Bit Detection
  • Complete Status Reporting Capabilities in Both Normal and Sleep Mode
  • Line Break Generation and Detection
  • Internal Test and Loopback Capabilities
  • Fully Prioritized Interrupt System Controls
  • Modem Control Functions (CTS\, RTS\, DSR\, DTR\, RI\, and CD\)
  • ST16C654 Pin Compatible With Additional Enhancements
  • Supports Up To 24-MHz Crystal Input Clock ( 1.5 Mbps)
  • Supports Up To 48-MHz Oscillator Input Clock ( 3 Mbps) for 5-V Operation
  • Supports Up To 32-MHz Oscillator Input Clock ( 2 Mbps) for 3.3-V Operation
  • 64-Byte Transmit FIFO
  • 64-Byte Receive FIFO With Error Flags
  • Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA and Interrupt Generation
  • Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control
  • Software/Hardware Flow Control
    • Programmable Xon/Xoff Characters
    • Programmable Auto-RTS\ and Auto-CTS\
  • Optional Data Flow Resume by Xon Any Character
  • DMA Signalling Capability for Both Received and Transmitted Data
  • Supports 3.3-V or 5-V Supply
  • Characterized for Operation From –40°C to 85°C
  • Software Selectable Baud Rate Generator
  • Prescalable Provides Additional Divide by 4 Function
  • Fast Access 2 Clock Cycle IOR\/IOW\ Pulse Width
  • Programmable Sleep Mode
  • Programmable Serial Interface Characteristics
    • 5, 6, 7, or 8-Bit Characters
    • Even, Odd, or No Parity Bit Generation and Detection
    • 1, 1.5, or 2 Stop Bit Generation
  • False Start Bit Detection
  • Complete Status Reporting Capabilities in Both Normal and Sleep Mode
  • Line Break Generation and Detection
  • Internal Test and Loopback Capabilities
  • Fully Prioritized Interrupt System Controls
  • Modem Control Functions (CTS\, RTS\, DSR\, DTR\, RI\, and CD\)

The TL16C754B is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C754B offers enhanced features. It has a transmission control register (TCR) that stores received FIFO threshold level to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.

The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and software flow control and hardware flow control capabilities.

The TL16C754B is available in 80-pin TQFP and 68-pin PLCC packages.

The TL16C754B is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C754B offers enhanced features. It has a transmission control register (TCR) that stores received FIFO threshold level to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.

The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and software flow control and hardware flow control capabilities.

The TL16C754B is available in 80-pin TQFP and 68-pin PLCC packages.
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種類 タイトル 最新の英語版をダウンロード 日付
* エラッタ TL16C754B Errata 2006年 8月 2日
* データシート TL16C754B: Quad UART with 64-Byte FIFO データシート (Rev. A) 2004年 6月 8日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点

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