패키징 정보
| 패키지 | 핀 WQFN (RUY) | 28 |
| 작동 온도 범위(°C) -40 to 125 |
| 패키지 수량 | 캐리어 5,000 | LARGE T&R |
DRV8328의 주요 특징
- 65-V Three Phase Half-Bridge Gate Driver
- Drives 3 High-Side and 3 Low-Side N-Channel MOSFETs (NMOS)
- 4.5 to 60-V Operating Voltage Range
- Supports 100% PWM Duty Cycle with Trickle Charge pump
- Bootstrap based Gate Driver Architecture
- 1000-mA Maximum Peak Source Current
- 2000-mA Maximum Peak Sink Current
- Hardware interface provides simple configuration
- Ultra-low power sleep mode <1 uA at 25 ̊C
- 4-ns (typ) propagation delay matching between phases
- Independent driver shutdown path (DRVOFF)
- 65-V tolerant wake pin (nSLEEP)
- Supports negative transients upto -10V on SHx
- 6x and 3x PWM Modes
- Supports 3.3-V, and 5-V Logic Inputs
- Accurate LDO (AVDD), 3.3 V ±3%, 80 mA
- Compact QFN Packages and Footprints
- Adjustable VDS overcurrent threshold through VDSLVL pin
- Adjustable deadtime through DT pin
- Efficient System Design With Power Blocks
- Integrated Protection Features
- PVDD Undervoltage Lockout (PVDDUV)
- GVDD Undervoltage (GVDDUV)
- Bootstrap Undervoltage (BST_UV)
- Overcurrent Protection (VDS_OCP, SEN_OCP)
- Thermal Shutdown (OTSD)
- Fault Condition Indicator (nFAULT)
DRV8328에 대한 설명
The DRV8328 family of devices is an integrated gate driver for three-phase applications. The devices provide three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The device generates the correct gate drive voltages using an internal charge pump and enhances the high-side MOSFETs using a bootstrap circuit. A trickle charge pump is included to support 100% duty cycle. The Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A sink. The DRV8328 can operate from a single power supply and supports a wide input supply range of 4.5 to 60 V.
The 6x and 3x PWM modes allow for simple interfacing to controller circuits. The device has integrated accurate 3.3-V LDO that can be used to power external controller and can be used as reference for CSA. The configuration settings for the device are configurable through hardware (H/W) pins.
A low-power sleep mode is provided to achieve low quiescent current by shutting down most of the internal circuitry. Internal protection functions are provided for undervoltage lockout, GVDD fault, MOSFET overcurrent, MOSFET short circuit, and overtemperature. Fault conditions are indicated on nFAULT pin.