DS91C180
- DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
- Optimal for ATCA, uTCA Clock Distribution Networks
- Meets or Exceeds TIA/EIA-899 M-LVDS Standard
- Wide Input Common Mode Voltage for Increased Noise Immunity
- DS91D180 has Type 1 Receiver Input
- DS91C180 has Type 2 Receiver Input for Fail-Safe Functionality
- Industrial Temperature Range
- Space Saving SOIC-14 Package (JEDEC MS-012)
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The DS91D180 and DS91C180 are 100 MHz M-LVDS (Multipoint Low Voltage Differential Signaling) line driver/receiver pairs designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancments that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.
The DS91D180/DS91C180 driver input accepts LVTTL/LVCMOS signals and converts them to differential M-LVDS signal levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and converts them to 3V LVCMOS signals. The DS91D180 device has a M-LVDS type 1 receiver input with no offset.The DS91C180 device has a type 2 receiver input which enable failsafe functionality.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair datasheet (Rev. M) | 2013/04/18 | |
| Application brief | How Far, How Fast Can You Operate MLVDS? | 2018/08/06 | ||
| Application note | Designing an ATCA Compliant M-LVDS Clock Distribution Network (Rev. B) | 2013/04/26 | ||
| Application note | Introduction to M-LVDS (TIA/EIA-899) (Rev. A) | 2013/01/03 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치