인터페이스 LVDS, M-LVDS 및 PECL

SN65LVDM22

활성

듀얼 멀티플렉스 LVDM 리피터

제품 상세 정보

Function Repeater Protocols LVDM, LVDS Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 250 Input signal LVDM Output signal LVDM Rating Catalog Operating temperature range (°C) -40 to 85
Function Repeater Protocols LVDM, LVDS Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 250 Input signal LVDM Output signal LVDM Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard
  • Designed for Clock Rates up to 200 MHz (400 Mbps)
  • Designed for Data Rates up to 250 Mbps
  • Pin Compatible With SN65LVDS122 and SN65LVDT122, 1.5 Gbps 2x2 Crosspoint Switch From TI
  • ESD Protection Exceeds 12 kV on Bus Pins
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Output Voltages of 350 mV Into:
    • 100- Load (SN65LVDS22)
    • 50- Load (SN65LVDM22)
  • Propagation Delay Time; 4 ns Typ
  • Power Dissipation at 400 Mbps of 150 mW
  • Bus Pins Are High Impedance When Disabled or With VCC Less Than 1.5 V
  • LVTTL Levels Are 5 V Tolerant
  • Open-Circuit Fail Safe Receiver

  • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard
  • Designed for Clock Rates up to 200 MHz (400 Mbps)
  • Designed for Data Rates up to 250 Mbps
  • Pin Compatible With SN65LVDS122 and SN65LVDT122, 1.5 Gbps 2x2 Crosspoint Switch From TI
  • ESD Protection Exceeds 12 kV on Bus Pins
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Output Voltages of 350 mV Into:
    • 100- Load (SN65LVDS22)
    • 50- Load (SN65LVDM22)
  • Propagation Delay Time; 4 ns Typ
  • Power Dissipation at 400 Mbps of 150 mW
  • Bus Pins Are High Impedance When Disabled or With VCC Less Than 1.5 V
  • LVTTL Levels Are 5 V Tolerant
  • Open-Circuit Fail Safe Receiver

The SN65LVDS22 and SN65LVDM22 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The receiver outputs can be switched to either or both drivers through the multiplexer control signals S0 and S1. This allows the flexibility to perform splitter or signal routing functions with a single device.

The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100- load.

The intended application of these devices and signaling technique is for both point-to-point baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).

The SN65LVDS22 and SN65LVDM22 are characterized for operation from –40°C to 85°C.

The SN65LVDS22 and SN65LVDM22 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The receiver outputs can be switched to either or both drivers through the multiplexer control signals S0 and S1. This allows the flexibility to perform splitter or signal routing functions with a single device.

The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100- load.

The intended application of these devices and signaling technique is for both point-to-point baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).

The SN65LVDS22 and SN65LVDM22 are characterized for operation from –40°C to 85°C.

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기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
4개 모두 보기
유형 직함 날짜
* Data sheet Dual Multiplexed LVDS Repeaters datasheet (Rev. C) 2002/05/09
Application note An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) PDF | HTML 2023/06/22
Application brief How Far, How Fast Can You Operate MLVDS? 2018/08/06
Application note SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) 2001/11/20

설계 및 개발

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시뮬레이션 모델

SN65LVDM22 IBIS Model

SLLM008.ZIP (33 KB) - IBIS Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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