SN54BCT8373A

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Product details

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family BCT Rating Military Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family BCT Rating Military Operating temperature range (°C) -55 to 125
CDIP (JT) 24 221.44 mm² 32 x 6.92 LCCC (FK) 28 130.6449 mm² 11.43 x 11.43
  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Octal Test-Integrated Circuits
  • Functionally Equivalent to 'F373 and 'BCT373 in the Normal-Function Mode
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • Test Operation Synchronous to Test Access Port (TAP)
  • Implement Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V) on TMS Pin
  • SCOPETM Instruction Set
    • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
    • Parallel Signature Analysis at Inputs
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic and Ceramic 300-mil DIPs (JT, NT)

    SCOPE is a trademark of Texas Instruments Incorporated.

     

  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Octal Test-Integrated Circuits
  • Functionally Equivalent to 'F373 and 'BCT373 in the Normal-Function Mode
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • Test Operation Synchronous to Test Access Port (TAP)
  • Implement Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V) on TMS Pin
  • SCOPETM Instruction Set
    • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
    • Parallel Signature Analysis at Inputs
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic and Ceramic 300-mil DIPs (JT, NT)

    SCOPE is a trademark of Texas Instruments Incorporated.

     

The 'BCT8373A scan test devices with octal D-type latches are members of the Texas Instruments SCOPETM testability integrated-
circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F373 and 'BCT373 octal D-type latches. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal latches.

In the test mode, the normal operation of the SCOPETM octal latches is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations, as described in IEEE Standard 1149.1-1990.

 

Four dedicated test terminals are used to control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54BCT8373A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT8373A is characterized for operation from 0°C to 70°C.

The 'BCT8373A scan test devices with octal D-type latches are members of the Texas Instruments SCOPETM testability integrated-
circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F373 and 'BCT373 octal D-type latches. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal latches.

In the test mode, the normal operation of the SCOPETM octal latches is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations, as described in IEEE Standard 1149.1-1990.

 

Four dedicated test terminals are used to control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54BCT8373A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT8373A is characterized for operation from 0°C to 70°C.

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Technical documentation

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Type Title Date
* Data sheet Scan Test Devices With Octal D-Type Latches datasheet (Rev. F) 01 Jul 1996
* SMD SN54BCT8373A SMD 5962-91725 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996

Design & development

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Simulation model

BSDL Model of SN74BCT8373A

SCTM004.ZIP (2 KB) - BSDL Model
Package Pins CAD symbols, footprints & 3D models
CDIP (JT) 24 Ultra Librarian
LCCC (FK) 28 Ultra Librarian

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