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SN54HCT74

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Dual D-type Positive-Edge-Triggered Flip-Flops With Clear And Preset

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Data sheet

SN54HCT74

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family HCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 25 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family HCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 25 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 14 130.4652 mm² 19.56 x 6.67 CFP (W) 14 58.023 mm² 9.21 x 6.3 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Operating voltage range of 4.5 V to 5.5 V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40-µA max I CC
  • Typical t pd = 17 ns
  • ±4-mA output drive at 5 V
  • Low input current of 1 µA max
  • Inputs are TTL-voltage compatible
  • Operating voltage range of 4.5 V to 5.5 V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40-µA max I CC
  • Typical t pd = 17 ns
  • ±4-mA output drive at 5 V
  • Low input current of 1 µA max
  • Inputs are TTL-voltage compatible

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
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Technical documentation

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Type Title Date
* Data sheet SNx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flips With Clear and Preset datasheet (Rev. G) PDF | HTML 21 Oct 2022
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Package Pins CAD symbols, footprints & 3D models
CDIP (J) 14 Ultra Librarian
CFP (W) 14 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
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