SN54LS273-SP

Name: SN54LS273-SP
Brand: TI
SKU: SN54LS273-SP
Price: 98.351 USD

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Octal D-type Flip-Flop With Clear

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Data sheet

document-pdfAcrobat Octal D-Type Flip-Flop With Clear--SN54273, SN54LS273, SN74273, SN74LS273 datasheet

SN54LS273-SP

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Data sheet

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Product details

Number of channels

8

Technology family

LS

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

Push-Pull

Clock frequency (max) (MHz)

35

IOL (max) (mA)

8

IOH (max) (mA)

-0.4

Supply current (max) (µA)

27000

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

-55 to 125

Rating

Space

Number of channels

8

Technology family

LS

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

Push-Pull

Clock frequency (max) (MHz)

35

IOL (max) (mA)

8

IOH (max) (mA)

-0.4

Supply current (max) (µA)

27000

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

-55 to 125

Rating

Space

CDIP (J)

20

167.464 mm² 24.2 x 6.92

Contains Eight Flip-Flops With Single-Rail Outputs
Buffered Clock and Direct Clear Inputs
Individual Data Input to Each Flip-Flop
Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators

Contains Eight Flip-Flops With Single-Rail Outputs
Buffered Clock and Direct Clear Inputs
Individual Data Input to Each Flip-Flop
Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ´273 and 10 milliwatts for the ´LS273.

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ´273 and 10 milliwatts for the ´LS273.

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