These devices each contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR\ and a count enable input CCKEN\. For cascading, a ripple carry output RCO\ is provided. Expansion is easily accomplished for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to CCK of the following stage.
Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | 8-Bit Binary Counters With Output Registers datasheet | 01 Mar 1988 | |
| * | SMD | SN54LS590 SMD 5962-87517 | 21 Jun 2016 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Designing with the SN54/74LS123 (Rev. A) | 01 Mar 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Oct 1996 | ||
| Application note | Live Insertion | 01 Oct 1996 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| CDIP (J) | 16 | Ultra Librarian |
| LCCC (FK) | 20 | Ultra Librarian |
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