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D-type flip-flops

SN74AHC273

ACTIVE

Octal D-Type Flip-Flops With Clear

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Data sheet

SN74AHC273

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 110 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 8 Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 110 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs Operating temperature range (°C) -40 to 125 Rating Catalog
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SOP (NS) 20 98.28 mm² 12.6 x 7.8 SSOP (DB) 20 56.16 mm² 7.2 x 7.8 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4
  • Operating range 2V to 5.5V VCC
  • Contain eight flip-flops with single-rail outputs
  • Direct clear input
  • Individual data input to each flip-flop
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
    • 1000V charged-device model (C101)
  • On products compliant to MIL-PRF-38535, All parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • Operating range 2V to 5.5V VCC
  • Contain eight flip-flops with single-rail outputs
  • Direct clear input
  • Individual data input to each flip-flop
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
    • 1000V charged-device model (C101)
  • On products compliant to MIL-PRF-38535, All parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

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Technical documentation

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Type Title Date
* Data sheet SNx4AHC273 Octal D-Type Flip-Flops With Clear datasheet (Rev. J) PDF | HTML 23 Jul 2024
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 Sep 1999
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Package Pins CAD symbols, footprints & 3D models
PDIP (N) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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Information included:
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