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SN74LV240A

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8-ch, 2V to 5.5V inverters with 3-state outputs

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Data sheet

SN74LV240A

ACTIVE
Data sheet Order now

Product details

Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SOP (NS) 20 98.28 mm² 12.6 x 7.8 SSOP (DB) 20 56.16 mm² 7.2 x 7.8 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4 VSSOP (DGS) 20 24.99 mm² 5.1 x 4.9
  • VCC operation of 2V to 5.5V
  • Max tpd of 6.5ns at 5V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
  • Support mixed-mode voltage operation on all ports
  • Latch-up performance exceeds 250mA per JESD 17
  • Ioff supports live insertion, partial power-down mode, and back drive protection
  • VCC operation of 2V to 5.5V
  • Max tpd of 6.5ns at 5V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
  • Support mixed-mode voltage operation on all ports
  • Latch-up performance exceeds 250mA per JESD 17
  • Ioff supports live insertion, partial power-down mode, and back drive protection

These octal buffers/drivers with inverted outputs are designed for 2V to 5.5V VCC operation.

The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

These octal buffers/drivers with inverted outputs are designed for 2V to 5.5V VCC operation.

The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
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Technical documentation

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* Data sheet SN74LV240A Octal Inverting Buffers/Drivers With 3-State Outputs datasheet (Rev. K) PDF | HTML 13 May 2024

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LV240A Behavioral SPICE Model

SCLM179.ZIP (7 KB) - PSpice Model
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Simulation model

SN74LV240A IBIS Model (Rev. A)

SCEM136A.ZIP (24 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOIC (DW) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
VSSOP (DGS) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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