ADC12DL2500
- ADC core:
- 12-Bit resolution
- Up to 1GSPS, 3GSPS, 5GSPS in single-channel mode
- Up to 500MSPS, 1.5GSPS, 2.5GSPS in dual-channel mode
- Internal dither for low-magnitude, high-order harmonics
- Low-latency LVDS interface:
- Total latency: < 10ns
- Up to 48 data pairs at 1.6Gbps
- Four DDR data clocks
- Strobe signals simplify synchronization
- Noise floor (no input, VFS = 1VPP-DIFF):
- Dual-channel mode: -143.5, -148, -149.8dBFS/Hz
- Single-channel mode: -146.2, -150.3, -152.2dBFS/Hz
- Buffered analog inputs with VCMI of 0V:
- Analog input bandwidth (–3dB): 8GHz
- Full-scale input voltage (VFS, default): 0.8VPP
- Noiseless aperture delay (TAD) adjustment:
- Precise sampling control: 19fs step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- Power consumption: 2.6, 2.8, 3W
The ADC12DL500, ADC12DL1500 and ADC12DL2500 are a family of analog-to-digital converters (ADC) that can sample up to 500MSPS, 1.5GSPS, and 2.5GSPS in dual-channel mode and up to 1GSPS, 3GSPS, and 5GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and sample rate (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications.
The devices uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | ADC12DLx500 0.5, 1.5, 2.5GSPS Dual-Channel or 1, 3, 5GSPS Single-Channel,12-Bit Analog-to-Digital Converters (ADC) With LVDS Interface datasheet | PDF | HTML | 2024年 1月 31日 |
| EVM User's guide | ADC12DLXX00 Evaluation Module User's Guide (Rev. A) | PDF | HTML | 2023年 12月 7日 | |
| Certificate | ADC12DL2500EVM EU Declaration of Conformity (DoC) | 2023年 11月 15日 |
設計與開發
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ADC12DL2500EVM — ADC12DL2500 評估模組
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCBGA (ACF) | 256 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。