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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADS5204-Q1

停產

雙通道、10 位元、40-MSPS 類比轉數位轉換器 - 符合汽車應用的需求

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ADS5204-Q1 已停止生產
此產品已停產。新設計應考量替代產品。
open-in-new 比較替代產品
功能相同，但引腳輸出與所比較的裝置不同
ADC10040-Q1 現行 10 位元 40-MSPS 類比轉數位轉換器 (ADC) - 符合汽車應用標準 This product is an enhanced stereo codec with enhanced digital effects
ADC10DL065 現行 雙通道、10 位元、65-MSPS 類比轉數位轉換器 (ADC) This product is an enhanced stereo codec with enhanced digital effects

ADS5204-Q1

停產
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產品詳細資料

Sample rate (max) (Msps) 40 Resolution (bps) 10 Number of input channels 2 Interface type Parallel CMOS, TTL Analog input BW (MHz) 300 Features Low Power Rating Automotive Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 275 Architecture Pipeline SNR (dB) 60.5 ENOB (bit) 9.7 SFDR (dB) 75 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 40 Resolution (bps) 10 Number of input channels 2 Interface type Parallel CMOS, TTL Analog input BW (MHz) 300 Features Low Power Rating Automotive Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 275 Architecture Pipeline SNR (dB) 60.5 ENOB (bit) 9.7 SFDR (dB) 75 Operating temperature range (°C) -40 to 85 Input buffer Yes
TQFP (PFB) 48 81 mm² 9 x 9
  • Qualified for Automotive Applications
  • 3.3-V Single-Supply Operation
  • Dual Simultaneous Sample-and-Hold Inputs
  • Differential or Single-Ended Analog Inputs
  • Programmable Gain Amplifier: 0 dB to 18 dB
  • Separate Serial Control Interface
  • Single or Dual Parallel Bus Output
  • 60-dB SNR at fIN = 10.5 MHz
  • 73-dB SFDR at fIN = 10.5 MHz
  • Low Power: 275 mW
  • 300-MHz Analog Input Bandwidth
  • 3.3-V TTL/CMOS-Compatible Digital I/O
  • Internal or External Reference
  • Adjustable Reference Input Range
  • Power-Down (Standby) Mode
  • TQFP-48 Package
  • APPLICATIONS
    • Digital Communications (Baseband Sampling)
    • Portable Instrumentation
    • Video Processing
  • Qualified for Automotive Applications
  • 3.3-V Single-Supply Operation
  • Dual Simultaneous Sample-and-Hold Inputs
  • Differential or Single-Ended Analog Inputs
  • Programmable Gain Amplifier: 0 dB to 18 dB
  • Separate Serial Control Interface
  • Single or Dual Parallel Bus Output
  • 60-dB SNR at fIN = 10.5 MHz
  • 73-dB SFDR at fIN = 10.5 MHz
  • Low Power: 275 mW
  • 300-MHz Analog Input Bandwidth
  • 3.3-V TTL/CMOS-Compatible Digital I/O
  • Internal or External Reference
  • Adjustable Reference Input Range
  • Power-Down (Standby) Mode
  • TQFP-48 Package
  • APPLICATIONS
    • Digital Communications (Baseband Sampling)
    • Portable Instrumentation
    • Video Processing

The ADS5204 is a dual 10-bit, 40 MSPS analog-to-digital converter (ADC). It simultaneously converts each analog input signal into a 10-bit, binary coded digital word up to a maximum sampling rate of 40 MSPS per channel. All digital inputs and outputs are 3.3-V TTL/CMOS compatible.

An innovative dual pipeline architecture implemented in a CMOS process and the 3.3-V supply results in very low power dissipation. In order to provide maximum flexibility, both top and bottom voltage references can be set from user-supplied voltages. Alternatively, if no external references are available, the on-chip internal references can be used. Both ADCs share a common reference to improve offset and gain matching. If external reference voltage levels are available, the internal references can be powered down independently from the rest of the chip, resulting in even greater power savings.

The ADS5204 also features dual, onboard programmable gain amplifiers (PGAs) that allow a setting of 0 dB to 18 dB to adjust the gain of each set of inputs in order to match the amplitude of the incoming signal.

The ADS5204 is characterized for operation from –40°C to +85°C and is available in a TQFP-48 package.

The ADS5204 is a dual 10-bit, 40 MSPS analog-to-digital converter (ADC). It simultaneously converts each analog input signal into a 10-bit, binary coded digital word up to a maximum sampling rate of 40 MSPS per channel. All digital inputs and outputs are 3.3-V TTL/CMOS compatible.

An innovative dual pipeline architecture implemented in a CMOS process and the 3.3-V supply results in very low power dissipation. In order to provide maximum flexibility, both top and bottom voltage references can be set from user-supplied voltages. Alternatively, if no external references are available, the on-chip internal references can be used. Both ADCs share a common reference to improve offset and gain matching. If external reference voltage levels are available, the internal references can be powered down independently from the rest of the chip, resulting in even greater power savings.

The ADS5204 also features dual, onboard programmable gain amplifiers (PGAs) that allow a setting of 0 dB to 18 dB to adjust the gain of each set of inputs in order to match the amplitude of the incoming signal.

The ADS5204 is characterized for operation from –40°C to +85°C and is available in a TQFP-48 package.
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類型 標題 日期
* Data sheet Dual 10-Bit 40-MSPS Low-Power ADC With PGA datasheet (Rev. A) 2008年 6月 23日

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
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  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
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