CD4098B
- Retriggerable/resettable capability
- Trigger and reset propagation delays independent of RX, CX
- Triggering from leading or trailing edge
- Q and Q\ buffered outputs available
- Separate resets
- Wide range of output-pulse widths
- 100% tested for maximum quiescent current at 20 V
- Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range):
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices."
- Applications:
- Pulse delay and timing
- Pulse shaping
- Astable multivibrator
CD4098B dual monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed-voltage timing application.
An external resistor (RX) and an external capacitor (CX) control the timing for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q\ terminals. The time delay from trigger input to output transition (trigger progagation delay) and the time delay from set input to output transition (reset progagation delay) are independent of RX and CX.
Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) input are provided for triggering from either edge of an input pulse. An unused +TR input should be tied to VSS. An unused (-TR) input should be tied to VDD. A RESET (on low level) is provided for immediate termination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be tied to VDD. However, if an entire section of the CD4098B is not used, its RESET should be tied to VSS. See Table 1.
In normal operation the circuit triggers (extends the output pulse one period) on the application of each new trigger pulse. For operation in the non-retriggerable mode, Q\ is connected to -TR when leading-edge triggering (+TR) is used or Q is connected to +TR when trailing-edge triggering (-TR) is used.
The time period (T) for this multivibrator can be approximated by: TX= ½ RXCX for CX 0.01 uF. Time periods as a function of RX for values of CX and VDD are given in Fig. 8. Values of T vary from unit to unit and as a function of voltage, temperature, and RXCX.
The minimum value of external resistance, RX, is 5 k. The maximum value of external capacitance, CX, is 100uF. Fig.9 shows time periods as a function of CX for values of RX and VDD.
The output pulse width has variations of ±2.5% typically, over the temperature range of -55°C to 125°C for CX= 1000 pF and RX= 100 k.
For power supply variations of ±5%, the output pulse width has variations of ±0.5% typically, for VDD= 10 V and 15 V and ±1% typically, for VDD= 5 V at CX= 1000 pF and RX= 5 k.
These types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
The CD4098B is similar to type MC14528.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | CD4098B Types datasheet (Rev. C) | 2004年 10月 29日 | |
Application note | Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) | PDF | HTML | 2020年 3月 13日 | |
Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
User guide | Signal Switch Data Book (Rev. A) | 2003年 11月 14日 | ||
Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001年 12月 3日 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
PDIP (N) | 16 | Ultra Librarian |
SOIC (D) | 16 | Ultra Librarian |
TSSOP (PW) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點