CD74HC138-Q1

Name: CD74HC138-Q1
Brand: TI
SKU: CD74HC138-Q1
Price: 0.181 USD

現行

汽車類高速 CMOS 邏輯 3 至 8 線路解碼器解多工器 (反相和非反相)

立即訂購

產品規格表

document-pdfAcrobat High-Speed CMOS Logic 3- to 8-Line Inverting Decoder/Demultiplexer datasheet (Rev. A) (英文)

CD74HC138-Q1

現行

產品規格表

立即訂購

產品詳細資料

Technology family

HC

Number of channels

1

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

160

Technology family

HC

Number of channels

1

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

160

SOIC (D)

16

59.4 mm² 9.9 x 6

Qualified for Automotive Applications
Select One of Eight Data Outputs Active Low
I/O Port or Memory Selector
Three Enable Inputs to Simplify Cascading
Typical Propagation Delay of 13 ns at V_CC = 5 V, C_L = 15 pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
2-V to 6-V V_CC Operation
High Noise Immunity; N_IL or N_IH = 30% of V_CC, V_CC = 5 V

Qualified for Automotive Applications
Select One of Eight Data Outputs Active Low
I/O Port or Memory Selector
Three Enable Inputs to Simplify Cascading
Typical Propagation Delay of 13 ns at V_CC = 5 V, C_L = 15 pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
2-V to 6-V V_CC Operation
High Noise Immunity; N_IL or N_IH = 30% of V_CC, V_CC = 5 V

The CD74HC138 is a high-speed silicon-gate CMOS decoder well suited to memory address decoding or data routing applications. This circuit features low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky TTL logic. The circuit has three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC138 will go low.

Two active-low and one active-high enables (E1, E2, and E3) are provided to ease the cascading of decoders. The decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads.

The CD74HC138 is a high-speed silicon-gate CMOS decoder well suited to memory address decoding or data routing applications. This circuit features low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky TTL logic. The circuit has three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC138 will go low.

Two active-low and one active-high enables (E1, E2, and E3) are provided to ease the cascading of decoders. The decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads.

filter

尋找其它數位解多工器和解碼器

下載