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CDC906

不推薦在新設計中採用

167-MHz、LVCMOS、客製編程的 3-PLL 時脈合成器、倍頻器和分頻器

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產品規格表
CDC906 不建議用於新設計
此產品將繼續向現有客戶提供。新設計應考量替代產品。
open-in-new 比較替代產品
可直接投入的替代產品，相較於所比較的裝置，具備升級功能
CDCE906 現行 167-MHz、LVCMOS、可編程的 3-PLL 時脈合成器/倍頻器/分頻器 CDCE906 is a P2P, drop-in replacement for CDC906

CDC906

不推薦在新設計中採用
產品規格表 立即訂購

產品詳細資料

Function Clock generator Output frequency (max) (MHz) 167 Input type Differential, LVCMOS, XTAL Output type LVCMOS Operating temperature range (°C) to Rating Catalog
Function Clock generator Output frequency (max) (MHz) 167 Input type Differential, LVCMOS, XTAL Output type LVCMOS Operating temperature range (°C) to Rating Catalog
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-PPM Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typical 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock)
  • Packaged in 20-Pin TSSOP
  • Factory Programmable for Customized Default Settings are Available. Contact TI Sales Fordes for Further Details.
  • APPLICATIONS
    • Digital TV
    • Printer / Scanner
    • Set Top Box
    • Video / Audio

Pro-Clock is a trademark of Texas Instruments.
  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-PPM Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typical 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock)
  • Packaged in 20-Pin TSSOP
  • Factory Programmable for Customized Default Settings are Available. Contact TI Sales Fordes for Further Details.
  • APPLICATIONS
    • Digital TV
    • Printer / Scanner
    • Set Top Box
    • Video / Audio

Pro-Clock is a trademark of Texas Instruments.

The CDC906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDC906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDC906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components is automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device provides customized applications. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDC906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDC906 is characterized for operation from 0°C to 70°C.

The CDC906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDC906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDC906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components is automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device provides customized applications. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDC906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDC906 is characterized for operation from 0°C to 70°C.
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類型 標題 日期
* Data sheet Programmable 3-PLL Clock Synthesizer / Multiplier / Divider datasheet (Rev. B) 2008年 2月 11日

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點