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CDCM7005

現行

可將參考時脈與 VCXO 同步的高性能、低相位雜訊、低偏斜時脈同步器

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產品規格表

CDCM7005

現行
產品規格表 立即訂購

產品詳細資料

Function Single-loop PLL Number of outputs 5 Output frequency (min) (MHz) 0 Output frequency (max) (MHz) 1500 Input type LVCMOS (REF_CLK), LVPECL (VCXO_CLK) Output type LVCMOS, LVPECL Supply voltage (min) (V) 3 Supply voltage (max) (V) 3.6 Features Programmable Delay Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Single-loop PLL Number of outputs 5 Output frequency (min) (MHz) 0 Output frequency (max) (MHz) 1500 Input type LVCMOS (REF_CLK), LVPECL (VCXO_CLK) Output type LVCMOS, LVPECL Supply voltage (min) (V) 3 Supply voltage (max) (V) 3.6 Features Programmable Delay Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 2
BGA (ZVA) 64 64 mm² 8 x 8 VQFN (RGZ) 48 49 mm² 7 x 7
  • High Performance LVPECL and LVCMOS PLL Clock Synchronizer
  • Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies up to 200 MHz
  • VCXO_IN Clock is Synchronized to One of the Two Reference Clocks
  • VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)
  • Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by ×1, /2, /3, /4, /6, /8, /16 on Each Output Individually
  • Efficient Jitter Cleaning From Low PLL Loop Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 µA to 3 mA
  • Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs
  • Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)
  • Frequency Hold-Over Mode Improves Fail-Safe Operation
  • Power-up Control Forces LVPECL Outputs to 3-State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • Packaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or 48-Pin QFN (RGZ)
  • Industrial Temperature Range –40°C to 85°C
  • High Performance LVPECL and LVCMOS PLL Clock Synchronizer
  • Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies up to 200 MHz
  • VCXO_IN Clock is Synchronized to One of the Two Reference Clocks
  • VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)
  • Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by ×1, /2, /3, /4, /6, /8, /16 on Each Output Individually
  • Efficient Jitter Cleaning From Low PLL Loop Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 µA to 3 mA
  • Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs
  • Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)
  • Frequency Hold-Over Mode Improves Fail-Safe Operation
  • Power-up Control Forces LVPECL Outputs to 3-State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • Packaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or 48-Pin QFN (RGZ)
  • Industrial Temperature Range –40°C to 85°C

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O

VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, and input selection are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C.

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O

VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, and input selection are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C.
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類型 標題 日期
* Data sheet CDCM7005 3.3-V High Performance Clock Synchronizer and Jitter Cleaner datasheet (Rev. G) PDF | HTML 2017年 8月 16日
* Radiation & reliability report CDCM7005MHFG-V Radiation Test Report 2014年 11月 12日
EVM User's guide TSW3070EVM: Amplifier Interface to Current Sink DAC - (Rev. A) 2016年 5月 23日
User guide GC5325 System Evaluation Kit (Rev. F) 2011年 4月 20日
Application note TLK313x/CDCM7005 Multi-hop Performance 2009年 11月 1日
EVM User's guide TSW4100EVM User's Guide (Rev. A) 2008年 9月 16日
Product overview TSW3003: RF Transmit Signal Chain Demonstration Kit Bulletin 2006年 9月 28日
User guide CDCM7005 (BGA Package) Evaluation Module Manual (Rev. A) 2005年 12月 19日
EVM User's guide CDCM7005 (QFN Package) EVM Users Guide (Rev. A) 2005年 12月 19日
Application note Phase Noise/Phase Jitter Performance of CDCM7005 2005年 7月 26日
EVM User's guide CDCM7005 (QFN Package) EVM Manual 2005年 7月 14日
User guide CDCM7005 (BGA Package) Evaluation Module Manual 2005年 6月 27日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

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使用指南: PDF
TI.com 無法提供
開發板

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The DAC5688EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x/4x/8x interpolation filters, on-board clock multiplier and PLL, 32-bit NCO and (...)

使用指南: PDF
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模擬型號

CDCM7005 IBIS Model RGZ PKG With PKG Parasitics at 1kHz

SCAC062.ZIP (37 KB) - IBIS Model
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模擬型號

CDCM7005 IBIS Model RGZ PKG With PKG Parasitics at 2GHz (Rev. B)

SCAC061B.ZIP (43 KB) - IBIS Model
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模擬型號

CDCM7005 IBIS Model ZVA PKG With PKG Parasitics at 2GHz

SCAC060.ZIP (37 KB) - IBIS Model
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計算工具

CDC-CDCM7005-CALC — CDC7005 和 CDCM7005 PLL 迴路頻寬計算機

This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump (...)
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設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
立即進行設計
Gerber 檔案

CDCM7005BGA EVM Gerber Files

SCAC064.ZIP (669 KB)
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Gerber 檔案

CDCM7005QFN EVM Gerber Files

SCAC065.ZIP (567 KB)
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
參考設計

TIDA-01187 — 使用高速資料轉換器的光達脈衝飛時測距參考設計

Time-of-flight (ToF) optical methods for measuring distance with high precision are utilized in a variety of applications, such as laser safety scanners, range finders, drones, and guidance systems. This design details the advantages of a high-speed data-converter-based solution, including target (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00075 — 高頻寬和高電壓任意波形產生器前端

此設計展示如何使用 DAC5682Z 電流汲極輸出的主動介面，其中的典型應用包括任意波形產生器的前端。EVM 包括用於數位轉類比轉換的 DAC5682Z、用於示範使用超寬頻運算放大器的主動介面實作的 OPA695，以及展示具有大電壓擺幅的運算放大器的 THS3091 和 THS3095。電路板上也包括用於產生時脈的 CDCM7005、VCXO 和參考，以及用於電壓調節的線性穩壓器。與 EVM 的通訊可透過 USB 介面和 GUI 軟體完成。
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
BGA (ZVA) 64 Ultra Librarian
VQFN (RGZ) 48 Ultra Librarian
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