CDCVF25081
- Phase-locked loop based, zero-delay buffer
- 1 clock input to 2 banks of 4 outputs
- No external RC network required
- Supply voltage: 3 V to 3.6 V
- Operating frequency: 8 MHz to 200 MHz
- Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz
- Power-down mode available
- Current consumption: < 20 µA in
Power-down mode
- Current consumption: < 20 µA in
- 25-Ω on-chip series damping resistors
- Industrial temperature range: –40°C to 85°C
- Spread Spectrum Clock Compatible (SSC)
- Packaged in
- 9.9-mm × 3.91-mm, 16-pin SOIC (D)
- 5.0-mm × 4.4-mm, 16-pin TSSOP (PW)
The CDCVF25081 is a high performance, low skew, low jitter, phased-locked loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The outputs are divided into 2 banks for a total of 8 buffered CLKIN outputs. The device automatically puts the outputs to a low state when no CLKIN signal is present (power down mode).
The S1 and S2 pins allow selection between PLL or bypassed PLL outputs. When left open, the outputs are disabled to a logic low state.
The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The device operates in 3.3V supply environment and is characterized from –40°C to 85°C (ambient temperature).
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCVF25081 3.3-V Phased-Lock Loop Clock Driver datasheet (Rev. B) | PDF | HTML | 2022年 1月 12日 |
| Application note | Using TI's CDCVF2310 and CDCVF25081 with TLK1501 Serial Transceiver | 2003年 5月 14日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。