產品詳細資料

Function Single-ended Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
Function Single-ended Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • High-Performance 1:10 Clock Driver
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range = 2.3 V to 3.6 V
  • Input Clock Up To 200 MHz (See Figure 7)
  • Operating Temperature Range -40°C to 85°C
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five Outputs
  • Packaged in 24-Pin TSSOP
  • Pin-to-Pin Compatible to the CDCVF2310,
    Except the R = 22- Series Damping
    Resistors at Yn
  • APPLICATIONS
    • General-Purpose Applications

  • High-Performance 1:10 Clock Driver
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range = 2.3 V to 3.6 V
  • Input Clock Up To 200 MHz (See Figure 7)
  • Operating Temperature Range -40°C to 85°C
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five Outputs
  • Packaged in 24-Pin TSSOP
  • Pin-to-Pin Compatible to the CDCVF2310,
    Except the R = 22- Series Damping
    Resistors at Yn
  • APPLICATIONS
    • General-Purpose Applications

The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF310 is characterized for operation from -40°C to 85°C.

The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF310 is characterized for operation from -40°C to 85°C.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 1
類型 標題 日期
* Data sheet 2.5-V to 3.3-V High-Performance Clock Buffer datasheet (Rev. B) 2008年 1月 22日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

CDCVF310 IBIS Model (Rev. A)

SCAC058A.ZIP (22 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 24 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片