CY74FCT157T
- Function, Pinout, and Drive Compatible With FCT and F Logic
- Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
- Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
- Ioff Supports Partial-Power-Down Mode Operation
- Matched Rise and Fall Times
- Fully Compatible With TTL Input and Output Logic Levels
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- CY54FCT157T
- 32-mA Output Sink Current
- 12-mA Output Source Current
- CY74FCT157T
- 64-mA Output Sink Current
- 32-mA Output Source Current
- 3-State Outputs
The \x92FCT157T devices are quad two-input multiplexers that select four bits of data from two sources under the control of a common data-select (S) input. The output-enable (E\) input is active low. When E\ is high, all of the outputs (Y) are forced low, regardless of all other input conditions.
Moving data from two groups of registers to four common output buses is a common use of the \x92FCT157T devices. The state of S determines the particular register from which the data comes. It also can be used as a function generator. These devices are useful for implementing highly irregular logic by generating any 4 of the 16 different functions of 2 variables, with 1 variable common.
The \x92FCT157T devices are logic implementations of a four-pole, two-position switch, where the position of the switch is determined by the logic levels at S.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Quad 2-Input Multiplexers With 3-State Outputs datasheet (Rev. B) | 2001年 11月 2日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 2004年 6月 22日 | ||
| User guide | CYFCT Parameter Measurement Information | 2001年 4月 2日 | ||
| Selection guide | Advanced Bus Interface Logic Selection Guide | 2001年 1月 9日 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| SOIC (DW) | 16 | Ultra Librarian |
| SSOP (DBQ) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點