DS100MB203
- 10.3125 Gbps Dual Lane 2:1 Mux, 1:2 Switch or
Fan-Out - Low 390 mW Total Power (Typical)
- Advanced Signal Conditioning Features:
- Receive Equalization Up to 36 dB at 5 GHz
- Transmit De-Emphasis Up to –12 dB
- Transmit Output Voltage Control: 600 mV to
1300 mV
- Programmable Through Pin Selection, EEPROM
or SMBus Interface - Selectable 2.5-V or 3.3-V Supply Voltage
- –40°C to 85°C Operating Temperature Range
The DS100MB203 device is a dual port 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning suitable for 10GE, 10G-KR (802.3ap), Fibre Channel, PCIe, Infiniband, SATA3/SAS2 and other high-speed bus applications with data rates up to 10.3125 Gbps.
The continuous time linear equalizer (CTLE) of the receiver provides necessary boost to compensate up to 40” FR-4 or 10m cable (AWG-24) at 10.3125 Gbps - This on-chip feature eliminates the need for external signal conditioners. The transmitter features a programmable amplitude voltage levels to be selectable from 600 mVp-p to 1300 mVp-p and De-Emphasis of up to 12 dB.
The DS100MB203 can be configured to support PCIe, SAS/SATA, 10G-KR or other signaling protocols. When operating in 10G-KR and PCIe Gen-3 mode, the DS100MB203 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This seamless management of the link training protocol ensures system level interoperability with minimum latency.
The programmable settings can be applied through pin settings, SMBus (I2C) protocol or loaded directly from an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS100MB203 10.3125 Gbps Dual Lane 2:1/1:2 Mux/Buffer With Equalization and De-Emphasis datasheet (Rev. D) | PDF | HTML | 2016年 1月 19日 |
| Application note | Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) | 2023年 1月 31日 | ||
| Application note | Understanding EEPROM Programming for High Speed Repeaters and Mux Buffers | 2014年 10月 9日 | ||
| User guide | DS100MB203EVK User's Guide | 2012年 10月 17日 |
設計與開發
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DS100MB203EVK — 雙通道 2:1/1:2 多工器/緩衝器 SMA 評估套件
The DS100MB203EVK is a dual Lane 2:1/1:2 Mux/Buffer SMA evaluation kit. It provides a complete high bandwidth platform to evaluate the signal integrity and signal conditioning features of the DS100MB203SQ – 10.3125 Gbps Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis.
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (NJY) | 54 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。