DS92LV0421
- 5-Channel (4 Data + 1 Clock) Channel Link LVDS Parallel Interface Supports 24-Bit Data 3-Bit Control at 10 to 75 MHz
- AC-Coupled STP Interconnect Up to 10 m
- Integrated Terminations on Serializer and Deserializer
- At-Speed Link BIST Mode and Reporting Pin
- Optional I2C-Compatible Serial Control Bus
- Power-Down Mode Minimizes Power Dissipation
- 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
- >8-kV HBM
- –40° to 85°C Temperature Range
- Serializer (DS92LV0421)
- Data Scrambler for Reduced EMI
- DC-Balance Encoder for AC Coupling
- Selectable Output VOD and Adjustable De-Emphasis
- Deserializer (DS92LV0422)
- Fast Random Data Lock; No Reference Clock Required
- Adjustable Input Receiver Equalization
- EMI Minimization on Output Parallel Bus (SSCG and LVDS VOD Select)
The DS92LV042x chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair. The DS92LV042x enables applications currently using popular Channel Link or OpenLDI LVDS style devices to upgrade seamlessly to an embedded clock interface. This serial bus scheme reduces interconnect cost and eases design challenges. The parallel OpenLDI LVDS interface also reduces FPGA I/O pins, board trace count, and alleviates EMI issues when compared to traditional single-ended wide bus interfaces.
Programmable transmit de-emphasis, receive equalization, on-chip scrambling, and DC-balancing enables longer distance transmission over lossy cables and backplanes. The DS92LV0422 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy operation.
The DS92LV042x chipset is programmable through an I2C interface as well as through pins. A built-in, at-speed BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0421 and DS92LV0422 can be used interchangeably with the DS92LV2421 or DS92LV2422. This allows designers the flexibility to connect to the host device and receiving devices with different interface types: LVDS or LVCMOS.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS92LV042x 10-MHz to-75 MHz Channel Link II Serializer and Deserializer With LVDS Parallel Interface datasheet (Rev. D) | PDF | HTML | 2016年 12月 16日 |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018年 11月 9日 | ||
| Technical article | Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Ind | PDF | HTML | 2017年 8月 24日 | |
| Application note | DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) | 2013年 4月 29日 | ||
| User guide | LV04EVK01 Channel Link to Channel Link II Converter Evaluation Kit | 2012年 2月 1日 | ||
| Design guide | Channel Link II Design Guide | 2011年 1月 21日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (NJK) | 36 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點