DS92LV1260
- Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks
- Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams
- Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input
- Parallel Clock Rate up to 40MHz
- On Chip Filtering for PLL
- Absolute Maximum Worst Case Power Dissipation = 1.9W at 3.6V
- High Impedance Inputs Upon Power Off (Vcc = 0V)
- Single Power Supply at +3.3V
- 196-pin NFBGA Package (Low-profile Ball Grid Array) Package
- Industrial Temperature Range Operation: −40°C to +85°C
All trademarks are the property of their respective owners.
The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to six data streams that have been serialized by the Texas Instruments DS92LV1021 or DS92LV1023 Bus LVDS serializers. The device also includes a seventh serial input channel that serves as a redundant input.
Each deserializer block in the DS92LV1260 operates independently with its own clock recovery circuitry and lock-detect signaling.
The DS92LV1260 uses a single +3.3V power supply with a typical power dissipation of 1.2W at 3.3V with a PRBS-15 pattern. Refer to the Connection Diagrams for packaging information.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS92LV1260 Six Channel 10 Bit BLVDS Deserializer datasheet (Rev. F) | 2013年 4月 16日 | |
| Application note | How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A) | 2013年 4月 26日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| NFBGA (NZH) | 196 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。