LMH0031

現行

具視訊和輔助資料 FIFO 的數位視訊解串器/解碼器

產品詳細資料

Function Deserializer Supply voltage (V) 2.5, 3.3 Power consumption (mW) 705 Data rate (max) (Mbps) 1485 Control interface Pin/I2C Operating temperature range (°C) 0 to 70
Function Deserializer Supply voltage (V) 2.5, 3.3 Power consumption (mW) 705 Data rate (max) (Mbps) 1485 Control interface Pin/I2C Operating temperature range (°C) 0 to 70
TQFP (PAG) 64 144 mm² 12 x 12
  • SDTV/HDTV Serial Digital Video Standard Compliant
  • Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.485 Gbps Serial Video Data Rates with Auto-Detection
  • LSB De-Dithering Option
  • Uses Low-Cost 27MHz Crystal or Clock Oscillator Reference
  • Fast VCO Lock Time: < 500 µs at 1.485 Gbps
  • Built-in Self-Test (BIST) and Video Test Pattern Generator (TPG) Patent Applications Made or Pending
  • Automatic EDH/CRC Word and Flag Processing
  • Ancillary Data FIFO with Extensive Packet Handling Options
  • Adjustable, 4-Deep Parallel Output Video Data FIFO
  • Flexible Control and Configuration I/O Port
  • LVCMOS Compatible Control Inputs and Clock and Data Outputs
  • LVDS and ECL-Compatible, Differential, Serial Inputs
  • 3.3V I/O Power Supply and 2.5V Logic Power Supply Operation
  • Low Power: Typically 850mW
  • 64-Pin TQFP Package
  • Commercial Temperature Range 0°C to +70°C

All trademarks are the property of their respective owners.

  • SDTV/HDTV Serial Digital Video Standard Compliant
  • Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.485 Gbps Serial Video Data Rates with Auto-Detection
  • LSB De-Dithering Option
  • Uses Low-Cost 27MHz Crystal or Clock Oscillator Reference
  • Fast VCO Lock Time: < 500 µs at 1.485 Gbps
  • Built-in Self-Test (BIST) and Video Test Pattern Generator (TPG) Patent Applications Made or Pending
  • Automatic EDH/CRC Word and Flag Processing
  • Ancillary Data FIFO with Extensive Packet Handling Options
  • Adjustable, 4-Deep Parallel Output Video Data FIFO
  • Flexible Control and Configuration I/O Port
  • LVCMOS Compatible Control Inputs and Clock and Data Outputs
  • LVDS and ECL-Compatible, Differential, Serial Inputs
  • 3.3V I/O Power Supply and 2.5V Logic Power Supply Operation
  • Low Power: Typically 850mW
  • 64-Pin TQFP Package
  • Commercial Temperature Range 0°C to +70°C

All trademarks are the property of their respective owners.

The LMH0031 SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the LMH0031 include: clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and automatic video format determination. The parallel video output features a variable-depth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented.

The unique multi-functional I/O port of the LMH0031 provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the LMH0031 to the desired application. The LMH0031 is auto-configured to a default operating condition at power-on or after a reset command. Separate power pins for the PLL, deserializer and other functional circuits improve power supply rejection and noise performance.

The LMH0031 has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables comprehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD component video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all implemented rasters. The colour bar pattern has optional transition coding at changes in the chroma and luma bar data. The TPG data is output via the parallel data port.

The LMH0030, SMPTE 292M / 259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver, is the ideal complement to the LMH0031.

The LMH0031's internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipation is typically 850mW. The device is packaged in a 64-pin TQFP.

The LMH0031 SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the LMH0031 include: clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and automatic video format determination. The parallel video output features a variable-depth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented.

The unique multi-functional I/O port of the LMH0031 provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the LMH0031 to the desired application. The LMH0031 is auto-configured to a default operating condition at power-on or after a reset command. Separate power pins for the PLL, deserializer and other functional circuits improve power supply rejection and noise performance.

The LMH0031 has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables comprehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD component video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all implemented rasters. The colour bar pattern has optional transition coding at changes in the chroma and luma bar data. The TPG data is output via the parallel data port.

The LMH0030, SMPTE 292M / 259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver, is the ideal complement to the LMH0031.

The LMH0031's internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipation is typically 850mW. The device is packaged in a 64-pin TQFP.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 11
類型 標題 日期
* Data sheet LMH0031 SMPTE 292M/259M Dig Video Deserial/Descram w/Video & Ancillary Data FIFO datasheet (Rev. A) 2013年 4月 15日
Selection guide Broadcast and Professional Video Interface Solutions (Rev. E) 2017年 4月 5日
Application note AN-1334 The LMH0030 in Segmented Frames Applications (Rev. B) 2013年 4月 26日
Application note AN-1336 LMH0030 or LMH0031 Control Port Bussed Operation (Rev. B) 2013年 4月 26日
Application note AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) 2013年 4月 26日
Application note AN-2145 Power Considerations for SDI Products (Rev. B) 2013年 4月 26日
Application note AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) 2013年 4月 26日
Application note Enhancing LMH0031 Jitter Perf w/Easy-To-Use VCXOs (Rev. B) 2013年 4月 26日
Application note High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems 2009年 11月 12日
Application note LMH0030 (CLC030), LMH0031 (CLC031A) ‚Çô Frequently Asked Questions (FAQs) 2008年 8月 26日
Application note Timing is Everything ‚Çô The Broadcast Video Signal Path 2007年 8月 2日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TQFP (PAG) 64 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片