SN54107

現行

具有清除功能的雙路 J-K 正反器

立即訂購

產品規格表

document-pdfAcrobat Dual J-K Flip-Flops With Clear datasheet (英文)

SN54107

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

2

Technology family

TTL

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL

IOL (max) (mA)

-0.4

IOH (max) (mA)

16

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

2

Technology family

TTL

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL

IOL (max) (mA)

-0.4

IOH (max) (mA)

16

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

14

130.4652 mm² 19.56 x 6.67

Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs
Dependable Texas Instruments Quality and Reliability

Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs
Dependable Texas Instruments Quality and Reliability

The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.

The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.

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