SN54ALS259
- 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion With Storage
- Asynchronous Parallel Clear
- Active-High Decoder
- Enable/Disable Input Simplifies Expansion
- Expandable for n-Bit Applications
- Four Distinct Functional Modes
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the
clear () and enable
(G\) inputs as shown in the function table. In the addressable-latch
mode, data at the data-in terminal is written into the addressed
latch. The
addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G\ should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs.
The SN54ALS259 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS259 is characterized for operation from 0°C to 70°C.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 8-Bit Addressable Latches datasheet (Rev. A) | 1994年 12月 1日 | |
* | SMD | SN54ALS259 SMD 5962-88741 | 2016年 6月 21日 | |
Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022年 12月 15日 | |
Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997年 8月 1日 | ||
Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||
Application note | Live Insertion | 1996年 10月 1日 | ||
Application note | Advanced Schottky (ALS and AS) Logic Families | 1995年 8月 1日 |
設計與開發
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封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
CDIP (J) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點