SN65EPT21
- 1 ns Propagation Delay
- Fmax > 300MHz
- Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
- 24-mA TTL Output
- Built-In Temperature Compensation
- Drop-In Compatible to the MC10EPT21, MC100EPT21
- APPLICATIONS
- Data and Clock Transmission Over Backplane
- Signaling Level Conversion for Clock or Data
The SN65EPT21 is a differential PECL-to-TTL translator. It operates on +3.3 V supply and ground only. The device includes circuitry to maintain inputs at Vcc/2 when left open.
The VBB pin is a reference voltage output for the device. When the device is used in single-ended mode, the unused input should be tied to VBB. This reference voltage can also be used to bias the input when it is ac coupled. When it is used, place a 0.01µF decoupling capacitor between VCC and VBB. Also limit the sink/source current to < 0.5 mA to VBB. Leave VBB open when it is not used.
The SN65EPT21 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.
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檢視所有 2 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 3.3V ECL Differential Receiver datasheet | 2009年 2月 10日 | |
| Application note | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007年 10月 17日 |
設計與開發
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使用指南: PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| VSSOP (DGK) | 8 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
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