SN65LVDM31
- Designed for Signaling Rates
Up to 150 Mbps - Low-Voltage Differential Signaling With Typical Output Voltage of 700 mV and a 100-
Load - Propagation Delay Time of 2.3 ns, Typical
- Single 3.3-V Supply Operation
- One Driver's Power Dissipation at 75 MHz, 50 mW, Typical
- High-Impedance Outputs When Disabled or With VCC < 1.5 V
- Bus-Pin ESD Protection Exceeds 12 kV
- Low-Voltage CMOS (LVCMOS) Logic Input Levels Are 5-V Tolerant
The signaling rate is the number of voltage transitions that can be made per second.
The SN65LVDM31 incorporates four differential line drivers that implement the electrical characteristics
of low-voltage differential signaling. This product offers a low-power alternative to 5-V
PECL drivers with similar signal levels. Any of the four current-mode drivers will deliver a minimum
differential output voltage magnitude of 540 mV into a 100- load when enabled by either an
active-low or active-high enable input.
The intended application of this device and signaling technique is for both point-to-point and
multiplexed baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media and the noise coupling to the environment.
The SN65LVDM31 is characterized for operation from -40°C to 85°C.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | High Speed Differential Line Driver datasheet (Rev. C) | 2002年 2月 6日 | |
| Application note | An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) | PDF | HTML | 2023年 6月 22日 | |
| Application brief | How Far, How Fast Can You Operate MLVDS? | 2018年 8月 6日 | ||
| User guide | Low Voltage Differential Signaling (LVDS) Evaluation Module (EVM) for Quad Drive (Rev. C) | 2010年 2月 16日 | ||
| Application note | SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) | 2001年 11月 20日 | ||
| Application note | An Overview of LVDS Technology | 1998年 10月 5日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。