SN65LVDS822
- 4:27 LVDS-to-CMOS Deserializer
- Pixel Clock Range of 4 MHz to 54 MHz,
for Resolutions of 160 × 120 to 1024 × 600 - Special 2:27 Mode With 14x Sampling
Allows Using Just Two Data Lanes - Very Low EMI With 3-Way Selectable
CMOS Slew Rate - Supports Single 3.3-V Power Supply;
VDDIO Allows 1.8 V to
3.3 V for Flexible Panel Support - Clock Output is Rising or Falling Edge
- Bus-Swap Feature for Flexible PCB Layout
- Integrated Switchable Input Termination
- All Input Pins are Failsafe; ±3 kV
HBM ESD Protection - 7-mm × 7-mm 48-Pin VQFN With 0.5-mm
Pitch - Compatible With TIA/EIA-644-A Transmitters
The SN65LVDS822 is an advanced FlatLink™ low-voltage differential signal (LVDS) receiver designed on a modern CMOS process. The device has several unique features, including three selectable CMOS output slew rates, CMOS output voltage support of 1.8 V to 3.3 V, a pinout swap option, integrated differential termination (configurable), an automatic low-power mode, and deserialization modes of 4:27 and 2:27. The device is compatible with TI FlatLink™ transmitters such as the SN75LVDS83B, SN65LVDS93A, and standard industry LVDS transmitters that comply with TIA/EIA 644-A.
The SN65LVDS822 features an automatic low-power Standby Mode, activated when the LVDS clock is disabled. The device enters an even lower-power Shutdown Mode with a low voltage applied to pin SHTDN#.
The SN65LVDS822 is packaged in a 48-pin 7-mm × 7-mm Plastic Quad Flatpack No-Lead (QFN) with a 0.5-mm pin pitch, and operates through an industrial ambient temperature range of –40°C to 85°C.
A clock frequency range of 4 MHz to 54 MHz is supported in the standard 7× mode, which is to be used with LVDS data rates of 28 Mbps to 378 Mbps. The 14x mode supports 4 MHz to 27 MHz, for LVDS data rates of 56Mbps to 378 Mbps. The LVDS clock frequency always matches the CMOS output clock frequency. DC common mode voltage is monitored on clock line for normal operation. The device is designed to support resolutions as low as 1/16th VGA (160 × 120), and as high as 1024 × 600, with 60 frames per second and 24-bit color.
The SN65LVDS822 features an automatic low-power standby mode, activated when the LVDS clock is disabled. The device enters an even lower-power shutdown mode with a low voltage applied to pin SHTDN#. In both low-power modes, all CMOS outputs drive low. All input pins have fail-safe protection that prevents damage from occurring before power supply voltages are high and stable.
The SN65LVDS822 is packaged in a 48-pin 7-mm x 7-mm Plastic Quad Flatpack No-Lead (QFN) with a 0.5-mm pin pitch, and operates through an industrial ambient temperature range of –40°C to 85°C.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN65LVDS822 Flatlink™ LVDS Receiver datasheet (Rev. B) | PDF | HTML | 2014年 7月 29日 |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018年 11月 9日 | ||
| Technical article | Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Ind | PDF | HTML | 2017年 8月 24日 | |
| User guide | SN65LVDS822 User’s Guide (Rev. A) | 2013年 9月 30日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。