SN65LVDS93B-Q1
- AEC-Q100 Qualified for Automotive Applications
- Temperature Grade 3: –40°C to 85°C
- HBM ESD Classification 3
- CDM ESD Classification C6
- LVDS Display Series Interfaces Directly to LCD Display Panels With Integrated LVDS
- Package: 14-mm x 6.1-mm TSSOP
- 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect Directly to Low-Power, Low-Voltage Application and Graphic Processors
- Transfer Rate up to 85 Mpps (Mega Pixel Per Second); Pixel Clock Frequency Range 10 MHz to 85 MHz; Max 2.38 Gbps data rate supported
- Suited for Display Resolutions Ranging From HVGA up to HD With Low EMI
- Operates From a Single 3.3-V Supply and 170 mW (Typical) at 75 MHz
- 28 Data Channels Plus Clock in Low-Voltage TTL to 4 Data Channels Plus Clock Out Low-Voltage Differential
- Consumes Less Than 1 mW When Disabled
- Selectable Rising or Falling Clock Edge Triggered Inputs
- Support Spread Spectrum Clocking (SSC)
- Supports RGB 888 to LVDS I Conversion
The SN65LVDS93B-Q1 transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the DS90CR286A-Q1 and LCD panels with integrated LVDS receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93B-Q1 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.
The SN65LVDS93B-Q1 is characterized for operation over ambient air temperatures of –40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | SN65LVDS93B-Q1 10 MHz - 85 MHz Automotive 28-bit Flat Panel Display Link LVDS SerDes Transmitter datasheet (Rev. A) | PDF | HTML | 2018年 5月 15日 |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018年 11月 9日 | ||
| Application note | AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) | 2018年 8月 3日 | ||
| Technical article | How to select serializers and deserializers in HMI systems | PDF | HTML | 2018年 4月 24日 |
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