首頁 介面 LVDS、M-LVDS 和 PECL IC
首頁
介面
LVDS、M-LVDS 和 PECL IC

SN65LVEL11

現行

3.3-V PECL 1:2 扇出緩衝器

立即訂購
產品規格表

SN65LVEL11

現行
產品規格表 立即訂購

產品詳細資料

Function Translator Protocols ECL, PECL Number of transmitters 2 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 4000 Input signal PECL Output signal ECL, PECL Rating Catalog Operating temperature range (°C) -40 to 85
Function Translator Protocols ECL, PECL Number of transmitters 2 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 4000 Input signal PECL Output signal ECL, PECL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • 1:2 ECL Fanout Buffer
  • Operating Range
    • PECL VCC = 3.0 V to 3.8 V With
      VEE = 0 V
    • NECL: VCC = 0 V with VEE = -3.0
      to -3.8V
  • 5 ps Skew Between Outputs
  • Support for Clock Frequencies > 2.0 GHz
  • 265 ps Typical Propagation Delay
  • Deterministic Output Value for Open Input Conditions or When Inputs = VEE
  • Built-in Temperature Compensation
  • Drop in Compatible to MC10LVEL11, MC100LVEL11
  • Built-In Input Pull Down Resistors
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion
  • 1:2 ECL Fanout Buffer
  • Operating Range
    • PECL VCC = 3.0 V to 3.8 V With
      VEE = 0 V
    • NECL: VCC = 0 V with VEE = -3.0
      to -3.8V
  • 5 ps Skew Between Outputs
  • Support for Clock Frequencies > 2.0 GHz
  • 265 ps Typical Propagation Delay
  • Deterministic Output Value for Open Input Conditions or When Inputs = VEE
  • Built-in Temperature Compensation
  • Drop in Compatible to MC10LVEL11, MC100LVEL11
  • Built-In Input Pull Down Resistors
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion

The SN65LVEL11 is a fully differential 1:2 ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in open condition. The SN65LVEL11 is functionally equivalent to SN65EL11 with improved performance. The SN65LVEL11 is housed in an industry standard SOIC-8 package and is also available in the TSSOP-8 package option.

The SN65LVEL11 is a fully differential 1:2 ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in open condition. The SN65LVEL11 is functionally equivalent to SN65EL11 with improved performance. The SN65LVEL11 is housed in an industry standard SOIC-8 package and is also available in the TSSOP-8 package option.
filter 尋找其它 LVDS、M-LVDS 和 PECL IC
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 1
類型 標題 日期
* Data sheet SN65LVEL11 datasheet 2008年 12月 8日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

SN65LVEL11 IBIS Model Version 1.1

SLLM049.ZIP (15 KB) - IBIS Model
下載
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
View Options
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片