SN65MLVD129
- LVTTL Receiver and Eight Line Drivers Configured as an 8-Port M-LVDS Repeater—SN65MLVD128
- 2 LVTTL Receivers and Eight Line Drivers Configured as Dual 4-Port M-LVDS Repeaters—SN65MLVD129
- Drivers Meet or Exceed the M-LVDS Standard (TIA/EIA-899)
- Low-Voltage Differential 30-
Line Drivers for Data Rates¹ Up to 250 Mbps or Clock Frequencies Up to 125 MHz - Power Up/Down Glitch Free
- Controlled Driver Output Voltage Transition Times for Improved Signal Quality
- Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V
- Independent Enables for each Driver
- Output-to-Ouput Skew tsk(o) ≤ 160 ps
Part-to-Part Skew tsk(pp) ≤ 800 ps - Single 3.3-V Voltage Supply
- Bus Pin ESD Protection Exceeds 9 kV
- Packaged in 48-Pin TSSOP (DGG)
- APPLICATIONS
- AdvancedTCA™ (ATCA™) Clock Bus Driver
- Clock Distribution
- Data and Clock Repeating Over Backplanes and Cables
- Cellular Base Stations
- Central Office Switches
- Network Switches and Routers
¹The data rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
AdvancedTCA and ATCA are trademarks of the PCI Industrial Computer Manufacturers Group.
The SN65MLVD128 and SN65MLVD129 are LVTTL-to-M.LVDS translators/repeaters. Outputs comply with the M.LVDS standard (TIA/EIA-899) and are optimized for data rates up to 250 Mbps, and clock frequencies up to 125 MHz. The driver outputs have been designed to support multipoint buses presenting loads as low as 30 and incorporates controlled transition times for backbone operation.
M-LVDS compliant devices allow for 32 nodes on a common bus, providing a high-speed replacement for RS-485 devices when lower common-mode voltage range and lower output signaling levels are acceptable. The SN65MLVD128 and SN65MLVD129 provide separate driver enables, allowing for independent control of each output signal.
Intended applications for these devices include transmission of clock signals from a central clock module, as well as translation and buffering of data or control signals for transmission through a controlled impedance backplane or cable.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN65MLVD128/129 - 1:8 LVTTL to M-LVDS Repeater, Dual 1:4 LVTTL to M-LVDS Repeate datasheet | 2003年 9月 4日 | |
| Application note | An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) | PDF | HTML | 2023年 6月 22日 | |
| Application brief | How Far, How Fast Can You Operate MLVDS? | 2018年 8月 6日 | ||
| Application note | SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) | 2001年 11月 20日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 48 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。